数字IC设计资料(IC前端|FPGA|ASIC) 今日: 1 |主题: 26621|排名: 5

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[资料] Advanced Verification Topics ...2 3 4 5	baddy2323 2012-9-22	4118575	dengqing1002 2024-10-11 14:59
Principles of Verifiable RTL Design.2nd.Edition.pdf ...2 3	chiguoquan 2009-8-30	205231	azzzztec 2024-10-11 03:25
[资料] 【强烈推荐】跟Xilinx SAE 学HLS系列视频讲座-跟我学HLS ...2 3 4 5 6..13	suisuisi 2020-4-26	12033104	lusiyuan 2024-10-10 19:54
[求助] VCS仿真卡住，无法生成verdi波形文件 - [已解决] ...2	hwhhyh25 2021-2-15	1313783	liuyuanhuiHUST 2024-10-10 14:36
[资料] Verilog语言的IEEE标准（2005版） ...2 3	catannie 2016-10-18	2512860	ic886 2024-10-10 10:48
[2008 6月新书] CMOS SRAM Circuit Design and Parametric Test ...2 3 4 5 6..31	jacocobi 2008-6-3	30665850	hbz2010 2024-10-10 09:54
[资料] M3 M0交换学习资料	ASIC88TOM 2024-7-26	61587	fengsui 2024-10-10 05:35
[资料] signed 2's complement 和signed 1's complement 区别	浪海 2020-6-30	44363	catannie 2024-10-9 19:00
cadence版图设计教程和仿真教程 ...2 3 4 5 6..63	kongchau 2008-12-18	62996797	i0977454522 2024-10-9 16:32
[资料] 综合与时序分析的设计约束 Synopsys设计约束(SDC).pdf ...2	tengjiexx 2023-5-6	126229	PYGH 2024-10-8 19:34
[资料] 基于FPGA的软件无线电DDC设计 ...2 3 4 5 6..7	智慧棒 2012-1-27	6023408	rfyong 2024-10-8 17:27
[资料] 时序约束和时序分析，看这两本就足够了 ...2 3 4 5 6..22	gooseman 2018-10-8	21371056	clslhy 2024-10-8 16:47
FPGA在软件无线电中的应用	cooperation 2007-4-1	82674	zhangming325 2024-10-8 16:09
[求助] 求问！Synopsys Designware库中数据是从哪个流程优化来的？	Moumo 2024-3-1	21463	Patrick0809 2024-10-8 15:53
[求助] verdi创建的.v文件导入报错，求解	木石 2017-9-5	55591	Patrick0809 2024-10-8 15:48
[求助] [求助] synopsys的vcs安装有误——/bin/sh: 0: Illegal option -h	great_sun 2024-4-20	11232	Patrick0809 2024-10-8 14:50
[资料] 基于FPGA的软件无线电高级培训班的精品资料 ...2	智慧棒 2011-8-21	195846	zhangming325 2024-10-8 14:21
[资料] FPGA-Verilog学习之红外接收解码_红外接收源码	明德扬教育 2017-8-3	73802	keenboyee 2024-10-8 11:08
Xilinx的FPGA设计全流程：Modelsim－Synplify.Pro－ISE.rar ...2 3 4 5 6..31	chengzhenjun 2007-3-31	30450607	ic886 2024-10-7 22:38
[资料] JESD79-4B，欢迎下载！ ...2	litaoilet 2022-11-24	102802	clslhy 2024-10-7 21:59
[资料] low power design ...2 3 4 5	Avalon 2016-1-26	4411731	clslhy 2024-10-7 21:55
[资料] synopsys designware ahci sata databook ...2	sunfire 2012-5-21	169707	clslhy 2024-10-7 21:18
[资料] Verilog设计教程-夏宇闻.pdf	tengjiexx 2023-5-6	83025	NANHU_BRUCE 2024-10-6 18:45
[资料] Designing with Xilinx FPGAs_ Using Vivado》 ...2 3 4 5 6	lanzhang 2021-1-2	5820273	tomedavid 2024-10-6 11:28
[资料] Advanced HDL Synthesis and SOC Prototyping ...2 3	xiaohaolaoda 2021-8-25	267577	zhb9103 2024-10-5 20:18
[资料] Computer Arithmetic--Algorithms and Hardware Designs--2nd Edition ...2	kl_upc 2024-5-24	165631	zhb9103 2024-10-5 20:17
[资料] Synopsys和Cadence最新软件网盘分享4(13年11月更新) ...2 3 4 5 6..10	504472832 2013-11-6	9851579	robinfit01 2024-10-5 18:41
Advanced Computer Architecture and.Parallel Processing.pdf ...2 3 4 5	ching 2009-3-12	4611896	zhb9103 2024-10-5 12:37
[资料] verilog代码	齐天大胜 2024-6-5	61832	cikulangsat 2024-10-3 16:01
[原创] USB Sniffer 一个开源的USB协议analyzer	dodoee 2024-8-14	12579	cikulangsat 2024-10-3 15:54
[原创] VERISILICON_SMIC13_V1.0 ...2 3 4 5 6..8	amonghsh006 2011-7-22	7933759	igolaps 2024-10-2 21:35
Cadence SpectreRF PowerPoint file ...2 3 4	hi_china59 2009-9-7	3111526	igolaps 2024-10-2 17:40
[原创] vivado时序约束编写笔记 ...2 3	Baoli 2023-10-14	224865	jsncepu 2024-9-30 20:16
ic前端几本经典书籍推荐 ...2 3 4 5 6..19	chevalier 2006-3-25	18356689	cmmjava 2024-9-30 13:51
[原创] a review of IGBT models ...2	anjiao 2012-12-15	114910	clslhy 2024-9-30 10:06

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