verilog hdl 和vhdl哪一个以后比较有用呀？请各位大侠指教

ytwu001

1800-2005 IEEE Standard for System Verilog: Unified Hardware Design, Specification and Verification Language


A set of extensions to the IEEE P1364 Verilog® Hardware Description Language to aid in the reaction and verification of abstract architectural level models. Includes design specification methods, embedded assertions language, test bench language including coverage and an assertions API, and a direct programming interface. Enables a productivity boost in design and validation, and covers design, simulation, validation, and formal assertion based verification flows.

Keywords: Assertions, Design Automation, Design Verification, Hardware Description Language (HDL), Verilog, Programming Language Interface (PLI), Verilog Programming Interface (VPI), SystemVerilog
Contents:

yinchyang

作为语言，其实二者没有明显的优劣，不过要跟工作环境有关，如果公司里
都用VHDL, 即便自己熟悉verilog,也只能转成verilog了。
感觉国内IC设计verilog用得比较多，而做FPGA/CPLD的有不少人在用VHDL。

power-twq

VERILOG  有用， 目前全世界绝大多数的工程师都在使用 VERILOG。

wusite

听说是verilog用的比较多

wodenaodai

不 我支持 VHDL

grace_yudy

估计这两个以后都没多大的用...随着工具越来越能干

ttkkxx

好东西，支持！！！！！！！

55555

看来还是支持verilog的人多

lxq124lxq

都学会吧,其实不难的

yangyuf

我个人觉得verilog比较好