关于verilog语句中的延时

amormio124

写#1这样的delay是不可综合的，
调用delay cell是可以综合的。

zzczx

"调用delay cell是可以综合的。" 相当于gate level的调用了，也算可以综合吧。

jtyx

恩，应该是只用于仿真的

abnerliu

Delay in verilog is for simualtion.

Usually, it is used in 2 ways:
1. Testbench:
    Use delay to how data is sent to design.
2. Gate behavior:
    Due to difference between simulator engine,how signal's value is calculated
    is different, especially your syntax is combined  Flip-Flop and relative cone
    logic. So, usually , we will ad delay like this :
    always @(*) begin
        A <= #1 B+C;
    end
    The purpose of this "#1" is: we want to make A and "B+C" 's value   
    calculation time different to avoid simulator 's difference.
    ( simulator: for ex, verilog-xl, ncverilog, modelsim)
    (  Actually, some behavior in verilog-xl simulator is wrong.)

abnerliu

34# abnerliu

Another point is:

For same simulator engine, RTL and gate level 's simulation result  may be not the same, because you dunno how other people make standard cell library 's behavior, and "not safe" behavior may cause your gate level simualtion fail( even your rtl level simulation is correct)

sagegao

仿真用，不能综合

qq847941010

一般不可综合

shirley_4

在RTL级建模中，由于没有物理电路与延时语句相对应，所以时延语句是不可综合的。但是在行为级，可以使用延时对语句更好地模拟真实电路的行为。[img][img][/img][/img]

guide13579

支持一下啊啊

zhutoub

一般正规的公司的编码规范里会要求增加这个延时，  其实这个目的主要是为了同步设计的仿真，表达一下真实电路这里是有一个电路延时的。  这样产生波形的时候，信号会延迟时钟沿一点，对入门的人来说，就更为明确每个时钟周期里信号的赋值是什么。