Digital Logic Design Using Verilog: Coding and RTL Synthesis

yqnie · 发表于 2019-1-20 10:25:35

thks for sharing

20032616 · 发表于 2019-1-24 10:11:26

好资料，感谢分享

eric_2017 · 发表于 2019-3-15 11:09:14

thanks

kavin_sun · 发表于 2019-3-19 10:01:07

Thank you very much!

knlam1001 · 发表于 2019-3-25 14:24:38

Thanks for sharing

yaoqing88 · 发表于 2019-4-17 05:43:38

楼主资料呢

jimcmwang · 发表于 2019-9-27 01:06:28

SP-Digital-Logic-Design-Verilog-Coding-Synthesis.part1.rar
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SP-Digital-Logic-Design-Verilog-Coding-Synthesis.part2.rar
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SP-Digital-Logic-Design-Verilog-Coding-Synthesis.part3.rar
(15 MB, 下载次数: 1306 )

SP-Digital-Logic-Design-Verilog-Coding-Synthesis.part4.rar
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jimcmwang · 发表于 2019-9-27 01:08:41

SP-Digital-Logic-Design-Verilog-Coding-Synthesis.part1.rar
(15 MB, 下载次数: 1373 )

SP-Digital-Logic-Design-Verilog-Coding-Synthesis.part2.rar
(15 MB, 下载次数: 1393 )

SP-Digital-Logic-Design-Verilog-Coding-Synthesis.part3.rar
(15 MB, 下载次数: 1306 )
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SP-Digital-Logic-Design-Verilog-Coding-Synthesis.part4.rar
(4.54 MB, 下载次数: 699 )

hughs · 发表于 2019-12-1 14:24:24

谢谢

holliwood · 发表于 2019-12-2 22:41:13

谢谢分享

[原创] Digital Logic Design Using Verilog: Coding and RTL Synthesis

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