RTL Design Style Guide for Verilog HDL

banxuan · 发表于 2016-6-16 11:23:50

参考下，谢谢分享

秦时明月sw · 发表于 2016-7-1 08:50:45

谢谢分享

小科白菜 · 发表于 2016-8-1 11:12:23

感谢分享！！赞赞赞

lhwei2008 · 发表于 2016-8-2 01:23:21

小科白菜 · 发表于 2016-8-3 19:05:54

来自第2.1.1
In the case of function statements, latches will not be generated even if the conditions are
not completely defined. In this case, however, it behaves like a latch during simulation,
but logic gates generated by logic synthesis tools have the result of don’t care, so that it is
uncertain whether the value takes 0 or 1. As a result this description can be very hazardous since the RTL simulation and gate simulation results will no longer match.[2]
请问这一段可以这样理解吗：function语句内部的case就算是没有default语句，综合时也不会生成锁存器，但是仿真时，由综合器生成的逻辑门有无关的状态，所以会造成前仿真和后仿真不一致的情况？

小科白菜 · 发表于 2016-8-3 19:09:40

请问为什么function语句内尽管没有default语句也不会生成latch呢？这点很困惑，谢谢高人指点一下

yuanjinjie1984 · 发表于 2016-8-4 15:09:46

thanks

zxctja · 发表于 2016-8-4 16:00:34

谢谢分享

荒漠小草 · 发表于 2016-8-5 17:37:59

感谢楼主！

leonmsi · 发表于 2016-9-15 20:51:02

我下载不了，可惜

[资料] RTL Design Style Guide for Verilog HDL

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