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在Time Analyzer中在周期约束下会有一项Minimum period,在Help中的解释是“the minimum period value that will work based on the path with the maximum delay”,但我看不出来在下面列出来的maximum data path和这个值有什么关系,如下,有谁能指教下吗
Timing constraint: TS_mem_interface_top0_infrastructure_top0_clk_dcm0_clk0dcm_0 = PERIOD TIMEGRP "mem_interface_top0_infrastructure_top0_clk_dcm0_clk0dcm_0" TS_SYS_CLK HIGH 50%;
3097 paths analyzed, 580 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors)
Minimum period is 7.594ns.
--------------------------------------------------------------------------------
Slack: 0.145ns (requirement - (data path - clock path skew + uncertainty))
Source: mem_interface_top0/ddr1_top0/data_path0/data_read0/first_sdr_data_5 (FF)
Destination: ddr_controller_fsm0/read_dat_o_5 (FF)
Requirement: 2.000ns
Data Path Delay: 1.837ns (Levels of Logic = 0)
Clock Path Skew: -0.018ns (3.267 - 3.285)
Source Clock: clk90_int rising at 2.000ns
Destination Clock: clk_int falling at 4.000ns
Clock Uncertainty: 0.000ns
Maximum Data Path: mem_interface_top0/ddr1_top0/data_path0/data_read0/first_sdr_data_5 to ddr_controller_fsm0/read_dat_o_5
Delay type Delay(ns) Logical Resource(s)
---------------------------- -------------------
Tcko 0.374 mem_interface_top0/ddr1_top0/data_path0/data_read0/first_sdr_data_5
net (fanout=1) 1.261 u_data_o<5>
Tdick 0.202 ddr_controller_fsm0/read_dat_o_5
---------------------------- ---------------------------
Total 1.837ns (0.576ns logic, 1.261ns route)
(31.4% logic, 68.6% route)
--------------------------------------------------------------------------------
Slack: 0.203ns (requirement - (data path - clock path skew + uncertainty))
Source: mem_interface_top0/ddr1_top0/controller0/auto_ref_wait (FF)
Destination: ddr_controller_fsm0/u_addr_22 (FF)
Requirement: 4.000ns
Data Path Delay: 3.797ns (Levels of Logic = 3)
Clock Path Skew: 0.000ns
Source Clock: clk_int falling at 4.000ns
Destination Clock: clk_int rising at 8.000ns
Clock Uncertainty: 0.000ns
Maximum Data Path: mem_interface_top0/ddr1_top0/controller0/auto_ref_wait to ddr_controller_fsm0/u_addr_22
Delay type Delay(ns) Logical Resource(s)
---------------------------- -------------------
Tcko 0.374 mem_interface_top0/ddr1_top0/controller0/auto_ref_wait
net (fanout=8) 0.643 auto_ref_req
Tilo 0.288 ddr_controller_fsm0/CS_FSM_Out1111
net (fanout=3) 0.159 ddr_controller_fsm0/N5
Tilo 0.313 ddr_controller_fsm0/u_addr_mux0000<0>21
net (fanout=25) 1.707 ddr_controller_fsm0/N3
Tilo 0.313 ddr_controller_fsm0/u_addr_mux0000<22>1
net (fanout=1) 0.000 ddr_controller_fsm0/u_addr_mux0000<22>
Tdyck 0.000 ddr_controller_fsm0/u_addr_22
---------------------------- ---------------------------
Total 3.797ns (1.288ns logic, 2.509ns route)
(33.9% logic, 66.1% route)
--------------------------------------------------------------------------------
Slack: 0.266ns (requirement - (data path - clock path skew + uncertainty))
Source: mem_interface_top0/ddr1_top0/data_path0/data_read0/first_sdr_data_12 (FF)
Destination: ddr_controller_fsm0/read_dat_o_12 (FF)
Requirement: 2.000ns
Data Path Delay: 1.720ns (Levels of Logic = 0)
Clock Path Skew: -0.014ns (3.267 - 3.281)
Source Clock: clk90_int rising at 2.000ns
Destination Clock: clk_int falling at 4.000ns
Clock Uncertainty: 0.000ns
Maximum Data Path: mem_interface_top0/ddr1_top0/data_path0/data_read0/first_sdr_data_12 to ddr_controller_fsm0/read_dat_o_12
Delay type Delay(ns) Logical Resource(s)
---------------------------- -------------------
Tcko 0.374 mem_interface_top0/ddr1_top0/data_path0/data_read0/first_sdr_data_12
net (fanout=1) 1.144 u_data_o<12>
Tdick 0.202 ddr_controller_fsm0/read_dat_o_12
---------------------------- ---------------------------
Total 1.720ns (0.576ns logic, 1.144ns route)
(33.5% logic, 66.5% route)
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