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Requirements: 1. The candidate is preferred to be MSEE with minimum of 6 years, or BSEE with minimum of 8 years experience in digital ASIC/SOC design engineering.
2. The candidate should have good understanding on ASIC design flow and have good knowledge on multiple clocks design, proficient for AMBA(AXI/AHB/APB) bus. 3. Experience on SATA or WLAN is
plus. 4. The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, imaginative thinking and sophisticated analytical techniques, self-driven for quality and timely result, capability
to solve complex problems and makes some modifications to standard methods and decision-making on important technical areas.
Responsibility: The successful candidate will work with team members and apply his/her design techniques to work on different phases of complex logic design for ASIC/SOC project. |