深圳验证-芯得

jj_seu

Sr/MTS Design Verification Engineer @深圳上海
简历发  boss@hi-talent.com

Requirements:

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The candidate is preferred to be MSEE with minimum of 2 years, orBSEE with minimum of 4 years experience in digital asic/SOC designverification.  The candidate should have good understanding on ASIC/SOCdesign flow and should have:

1.    Good knowledge ofdesign verification methodology, such as VMM or OVM.

2.    Many experiences withsimulation model creation and the testbench build

3.    Strong RTL coding withverilog and familiar with front-end design flow

4.    Strong C/C++ softwaredevelopment experiences

5.    Be familiar withscripting language, such as Perl, C shell, Makefile.

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It is a plus if the candidate has one or more of the followingexperience/knowledge, such as X86/arm/8051 architecture, AMBA(AXI/AHB/APB) bus,USB(3.0/2.0/1.1; SSIC/HSIC/host/device/OTG) system, NAND Flash hostcontroller/BCH/double-data-rate interface, Universal Flash Storage, PCI-E/PCIbus, low power design, clock generation and control, SD/eMMC host controller,SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs(I2S/I2C/UART), Ethernet, JTAG, etc.

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Hands-on lab experience is another plus, able to understand and/oruse the use scopes, logic analyzers, has knowledge or skill of board-level labdebugging.

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The candidate is expected to exhibit good verbal and writtencommunication skills in both Chinese and English, imaginative thinking andsophisticated analytical techniques, self-driven for quality and timely result,capability  to solve complex problems and makes some modifications tostandard methods and decision-making on important technical areas.

Responsibility:

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The successful candidate will apply current functional verificationtechniques to perform and improve pre-silicon verification quality and productTime to Market for ASIC/SOC design.  He/She should be able to workindependently on various DV tasks and providing technical guidance to the DVteam. The candidate would involve technically in the porting/creation of the DVenvironment for the new design, block and chip level test plan creation and implementation,coverage analysis, and regression cleanup.

Best Regards

Jane.Jin 金娟

Principal Consultant & General Manager @ Hi-TalentConsulting Co.,Ltd.

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