FPGA新手,该用verilog 还是VHDL?

ljf538

使用后者

ljf538

很v了

Paul_Lee

什么是 tong qiu

Paul_Lee

不讨论用VHDL还是verilog的问题了，说说关于设计方法的问题吧

woochj

好书谢谢

Paul_Lee

不谢不谢

mingbaibu

个人觉得,verilog工业上用的比较多,适用于较大型设计,而VHDL偏重于小型设计.
感觉对电路的理解才更重要,而语言只是表述的工具,接触时间长了基本上都能很好掌握.
( 我本人学的是verilog)

Paul_Lee

明白明白了

yuanpin318

For me, I think verilog HDL is more easy to learn.

In RTL level, Verilog and VHDL is same if you can use them without language problem.

Why verilog is more popular is more popular? Verilog is more stronger in gate level. After synthesis, even you are using VHDL to write RTL, verilog netlist is still more popular.

If you only do FPGA, both are same.

But I recommend verilog, easier and more readable.

forlorm

国内一般做asic的用verilog，FPGA用VHDL