DDR3 Read Leveling

linghuqiubai

DDR3初始化时需要进行Write Leveling和Read Leveling校准，Write Leveling目的是将DQS与CK对齐，那Read Leveling呢？看过程需要读取MPR中的预定义01010101码流，我理解了一下，Read Leveling的目的有两种可能：
1. 将读回的DQS与DQ信号对齐
2. 将读回的不同字节的DQS信号之间进行对齐
请问哪个是正确的理解？万分感谢啊！

linghuqiubai

回复 1# linghuqiubai

仔细想了想，read leveling的目的应该是将DQS对齐到该字节组的8个DQ窗口的中央

751194032

read leveling 是用于对齐不同byte之间的dqs

linghuqiubai

回复 3# 751194032

能否详细解释一下read leveling的原理呢？
因为我查了一些资料，虽然没有明确讲原理，但理解上应该是对齐DQS和DQ的，而且没有管不同byte的DQS关系

qw342333

tongqiu

qw342333

read leveling = read eye training + gate training
read eye training = left bound search + dqsdbl adjust to deskew + right bound search  + make sure dqs rise in the midpoint of dq
gate traning for make gate rise align with dqs, because of phy rx is not enable power, so gate traning is to enable phy rx。 gate training steps are the same as write leveling

so you can see read leveling is for all bits dq deskew and make gate rise align with dqs
that's my understanding, mybe not right

linghuqiubai

回复 6# qw342333

Thank you very much!
In my understanding, read leveling includes several steps such as MPR reading and normal reading. For MPR reading, the memory controller reads "01010101" patterns from the MPR of the SDRAM, to aliagn the read DQS to the center of the valid DQ window. Then the memory controller writes some fixed pattern to the SDRAM and reads them back from the same location, to adjust the DQS phase more precisely. During the calibration, it needs to find the left bound and the right bound just as you have said, to define the valid data window.
This is my understanding now, maybe not correct as well...

linghuqiubai

回复 6# qw342333

I'm confused about the gate training step you said, could you explain more detaily? Thanks a lot!

kakarottotan

回复 1# linghuqiubai


    最近也在研究，诸多不懂

是你的固执

亲爱的前辈可不可以把你的DDR3 SDRAM ip发过来借我用用嘛，前辈你最好了