RTL Modeling with SystemVerilog for Simulation and Synthesis using SystemVerilog for ASIC and FPGA design

dubu113 · 发表于 2019-12-7 23:42:55

좋은 자료네요.

999 · 发表于 2019-12-9 11:40:28

see see

radiss · 发表于 2019-12-12 10:16:38

thanks for sharing

Kiss_Rose · 发表于 2019-12-13 10:04:00

感谢分享

ronald66 · 发表于 2019-12-14 15:53:25

thanks for sharing

david69 · 发表于 2019-12-29 17:09:42

好东西,感谢分享!!

risccpu · 发表于 2019-12-30 17:21:18

good reference。

jimcmwang · 发表于 2020-1-7 14:19:56

RTL_Modeling_with_SystemVerilo.pdf

11.52 MB, 下载次数: 598 , 下载积分: 资产 -4 信元, 下载支出 4 信元

Ralphjh · 发表于 2020-1-7 15:06:47

谢谢分享

Kidzami · 发表于 2020-1-8 16:38:07

Thanks

[资料] RTL Modeling with SystemVerilog for Simulation and Synthesis using SystemVerilog for ASIC and FPGA design