RTL Modeling with SystemVerilog for Simulation and Synthesis using SystemVerilog for ASIC and FPGA design

版图白白 · 发表于 2019-10-29 09:59:05

谢谢分享

omnik · 发表于 2019-10-29 22:28:34

thanks for sharing

hezudao · 发表于 2019-10-30 04:56:22

谢谢分享

totuwei · 发表于 2019-10-30 16:33:01

Thanks for sharing

clslhy · 发表于 2019-11-1 16:04:03

thanks for sharing

ibubapa · 发表于 2019-11-1 16:04:33

sayangcinta 发表于 2019-10-25 08:09
thanks for sharing

thanks for sharing

chriszbx · 发表于 2019-11-1 17:59:40

谢谢分享

gaeazzz · 发表于 2019-11-2 09:03:23

thanks

chnmy · 发表于 2019-11-3 09:20:21

thanks for sharing

kimillt · 发表于 2019-11-3 21:05:31

谢谢分享，大神的书，值得学习

[资料] RTL Modeling with SystemVerilog for Simulation and Synthesis using SystemVerilog for ASIC and FPGA design