RTL Modeling with SystemVerilog for Simulation and Synthesis using SystemVerilog for ASIC and FPGA design

jacky_wang · 发表于 2019-11-20 13:23:30

多谢分享。

yesnyes · 发表于 2019-11-21 09:35:27

感谢分享

crazytroll · 发表于 2019-11-21 15:08:39

Thanks for your share.

Adam千 · 发表于 2019-11-21 16:58:58

RTL Modeling with Systemverilog For Simulation and Synthesis: Using SystemVerilog for asic and FPGA Design
by Stuart Sutherland
Paperback, 488 pages
Copyright 2017, Sutherland hdl, Inc., Tualatin, Oregon

RTL_Modeling_with_SystemVerilo.pdf

11.52 MB, 下载次数: 516 , 下载积分: 资产 -4 信元, 下载支出 4 信元

hanyushui · 发表于 2019-11-22 21:18:32

看一看

wallacebooth · 发表于 2019-11-23 23:45:51

thanks a lot

dubu113 · 发表于 2019-11-27 22:39:32

a good book

minervisa · 发表于 2019-12-5 10:57:58

thank you for sharing

jxli99 · 发表于 2019-12-5 19:36:28

非常棒的书，等了很久了，终于有人分享了，十分感谢！

jxli99 · 发表于 2019-12-5 19:49:38

EEE 1685-2014 IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tool Flows. Thanks！

[资料] RTL Modeling with SystemVerilog for Simulation and Synthesis using SystemVerilog for ASIC and FPGA design

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