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RTL:
always@( posedge CLK_NSLP or negedge msys_rst_n )
if(~msys_rst_n)
r_wdtrstreq_n <= 3'b000;
else begin
r_wdtrstreq_n[2] <= WDTRSTREQ_N & ~SWRST & r_wdtrstreq_n[1];
r_wdtrstreq_n[1] <= WDTRSTREQ_N & ~SWRST & r_wdtrstreq_n[0];
r_wdtrstreq_n[0] <= WDTRSTREQ_N & ~SWRST;
end
cl_mux2 u_cl_mux2_0 (
.d0 (r_wdtrstreq_n[2] ), .d1 (SCANRESET), .s0 (MOD_SCAN), .y (SYSRST_N) );
cl_mux2 u_cl_mux2_1 (
.d0 (SYSRST_N), .d1 (MODERST1_N), .s0 (MOD_BI), .y (MODERST3_N) );
`define RC03LCD_REALCELL
module cl_mux2 (d0,d1,s0,y);
input d0,d1,s0;
output y;
`ifdef RC03LCD_REALCELL
TB9MUX2XC vc_cl_mux2 (.D0(d0),.D1(d1),.S0(s0),.Y(y));
`else
wire _d0,_d1; wire _s0; not (_s0,s0); and (_d0,_s0,d0); and (_d1,s0,d1); or (y,_d0,_d1);
`endif
endmodule
合成结果(有uniqify,下面是MUX部分):
cl_mux2_0 u_cl_mux2_0 ( .d0(r_wdtrstreq_n[2]), .d1(SCANRESET), .s0(MOD_SCAN), .y(SYSRST_N) );
cl_mux2_1 u_cl_mux2_1 ( .d0(SYSRST_N), .d1(MODERST1_N), .s0(MOD_BI), .y(MODERST3_N) );
module cl_mux2_0 ( d0, d1, s0, y );
input d0, d1, s0;
output y;
wire n1, n2;
TB9INVXC U1 ( .A(d0), .YB(n2) );
TB9ON21XL U3 ( .A0(s0), .A1(n2), .B(n1), .YB(y) );
TB9NAND2XP U2 ( .A(d1), .B(s0), .YB(n1) );
endmodule
module cl_mux2_1 ( d0, d1, s0, y );
input d0, d1, s0;
output y;
TB9MUX2XC vc_cl_mux2 ( .D0(d0), .D1(d1), .S0(s0), .Y(y) );
endmodule
疑问:
合成出的的gate,cl_mux2_0应该是和cl_mux2_1一样,用的我指定的gate,为什么它自己又合成了?
初步判断下来是是因为cl_mux2_0的D0端接的是数组的某一位,
请教有没有什么办法使得cl_mux2_0也用我指定的gate,谢谢!! |
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