做了几个时序电路的formality,发现都是FF failing,找不出什么原因,请前辈帮忙,谢谢
设置:
1 ##
2 set hdlin_ignore_full_case true
3 set hdlin_ignore_parallel_case false
4 set hdlin_warn_on_mismatch_message "FMR_ELAB-147"
5 set hdlin_error_on_mismatch_message true
6 set hdlin_unresolved_modules black_box
7 set hdlin_enable_hier_naming true
8 set verification_set_undriven_signals X
9 set verification_constant_prop_mode auto
10 man enable_multiplier_generation
======================================================================
1179 Compare point 269/FFY/ASYNC_FF failed (is not equivalent)
1180 Compare point 147/FFX/ASYNC_FF failed (is not equivalent)
1181 Compare point 298/FFY/ASYNC_FF failed (is not equivalent)
1182 Compare point 299/FFY/ASYNC_FF failed (is not equivalent)
1183 Compare point 300/FFY/ASYNC_FF failed (is not equivalent)
1184 Compare point 301/FFY/ASYNC_FF failed (is not equivalent)
1185 Compare point 291/FFY/ASYNC_FF failed (is not equivalent)
1186 Compare point 302/FFY/ASYNC_FF failed (is not equivalent)
1187
1188 ********************************* Verification Results *********************************
1189 Verification FAILED
1190 -------------------
1191 Reference design: r:/WORK/divider_dshift
1192 Implementation design: i:/WORK/divider_dshift
1193 590 Passing compare points
1194 20 Failing compare points
1195 0 Aborted compare points
1196 72 Unverified compare points
1197 ----------------------------------------------------------------------------------------
1198 Matched Compare Points BBPin Loop BBNet Cut Port DFF LAT TOTAL
1199 ----------------------------------------------------------------------------------------
1200 Passing (equivalent) 260 0 0 0 65 265 0 590
1201 Failing (not equivalent) 0 0 0 0 0 20 0 20
1202 Unverified 0 0 0 0 0 72 0 72
1203 ****************************************************************************************