generated clock设置问题

xuhaoee

Picture shows an example where the clockSYS_CLKis gated by the
output of a flip-flop. Since the output of the flip-flop may not be a constant,
one way to handle this situation is to define a generated clock at the output
of theandcell which is identical to the input clock.


将门控时钟设置成generated clock在STA操作中有什么好处和作用？求大神解答~~~

chengroc

1，利于分析UAND1的两个输入端的时序是否满足（若不满足则可能在CORE_CLK上产生glitch）
2，利于分析SYS_CLK和CORE_CLK这两个时钟域之间的path

楼下补充

hbaifenbai

是不是也可以方便得到源clock的latency