用VCS仿真xilinx mig的example design 出错

古镜子 · 发表于 2016-7-29 15:11:58

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用VCS来仿真xilinx生成的mig模块，一直出错。

配置信息如下：

os : Red hat 6.4

mig : mig 7 series v2.3

vcs : vcs-mx_vG-2012.09

Testbench from example design sim_tb_top.

Use script file : vcs_run.sh (auto generate).

结果:

"TEST FAILED: INITIALION DID NOT COMPLETE."

The result have some warnings:

Warning -[TFIPC] Two few instance port connections.

Warning -[PCWM-W] Port connection width mismatch.

Warning -[STASKW_CO] cannot open file

***** Warning: The analog data file design.txt for XADC instance sim_tb_top.u_ip_top.u_mig.u_mig_mig.temp_mon_enabled.u_tempmon.xadc_supplied_temperature.XADC_inst was not fond.Use the SIM_MONITOR_FILE parameter to specify the analog data file name or use the default name: design.txt.

OTHES warnings:

WARNING: 200 us is required before RST_N goes inactive.

WARNING: 500 us is required before RST_N goes inactive before CKE goes active.

有谁遇到过这个问题，求帮助？？？？