求高人指点

雪儿儿的脚步

我在读systemverilog for verification, 从http://chris.spear.net/systemverilog/#Examples， 下载的Utopia example。 我没有VCS， 所以用的是ModelSim SE PLUS 6.5， 但是编译时有错误，总是出现下面的问题：** Error: scoreboard.sv(60): (vlog-7027) Hierarchical reference ('top.squat.lut.read') not allowed from within a package.
** Error: D:/Program Files/yangshuang/modeltech_6.5/myproject/11-01.Example/environment.sv(86): (vlog-7027) Hierarchical reference ('top.squat.lut.read') not allowed from within a package.


** Error: utopia.sv(69): near "interface": syntax error, unexpected "interface", expecting "assert "
请问是编译问题吗？例如文件次序。还是编译器和vcs不一样造成的。求高人指点。

Ricky_22

model sim编译不是很方便，好像得加个什么选项的，具体的参考usr guide

雪儿儿的脚步

回复 2# Ricky_22 你好，真的非常感谢你回答了我的问题，现在已经急得火烧眉毛了。我在Modelsim SE 6.5的菜单栏里找到Compile，但是Compile Options是灰色的，不能点击的。还有你说的usr guide，我在Modelsim SE 6.5的菜单栏中没有找到。
你可以再说的具体点吗？谢谢了，非常感谢

Ricky_22

回复 3# 雪儿儿的脚步


   进你安装的目录，应该有个doc或者example，里面你查下应该就能看到文档，你可以参考example编译，里面应该会有个do的脚本

雪儿儿的脚步

回复 4# Ricky_22 嗨喽，你好。我在Modelsim SE 6.5的菜单栏的Help中找到了User's Manual，在其中的第277页的Incremental Compilation中看到这样一段英语描述：（第一段没什么用，重点在后面几段）
        ModelSim Verilog supports incremental compilation of designs. Unlike other Verilog
simulators, there is no requirement that you compile the entire design in one invocation of the
compiler.
      You are not required to compile your design in any particular order (unless you are using
SystemVerilog packages; see note below) because all module and UDP instantiations and
external hierarchical references are resolved when the design is loaded by the simulator.
     Note
     Compilation order may matter when using SystemVerilog packages. As stated in the

IEEE std 1800-2005 LRM, section entitled Referencing data in packages, which states:
"Packages must exist in order for the items they define to be recognized by the scopes in
which they are imported.”

      Incremental compilation is made possible by deferring these bindings, and as a result some
errors cannot be detected during compilation. Commonly, these errors include: modules that
were referenced but not compiled, incorrect port connections, and incorrect hierarchical
references.


      看了上面的描述以后，我觉得可能是编译顺序的问题，所以我就使用了自动生成编译顺序的方法，描述如下：
     Auto-Generating Compile Order
     Auto Generate is supported for HDL-only designs. The Auto Generate button in the Compile
Order dialog (see above) "determines" the correct compile order by making multiple passes
over the files. It starts compiling from the top; if a file fails to compile due to dependencies, it
moves that file to the bottom and then recompiles it after compiling the rest of the files. It
continues in this manner until all files compile successfully or until a file(s) can’t be compiled
for reasons other than dependency.
      Files can be displayed in the Project window in alphabetical or compile order (by clicking the
column headings). Keep in mind that the order you see in the Project tab is not necessarily the
order in which the files will be compiled.

    按照上述描述操作，编译以后还是出现之前的error：
   ** Error: scoreboard.sv(60): (vlog-7027) Hierarchical reference ('top.squat.lut.read') not allowed from within a package.
   ** Error: D:/Program Files/yangshuang/modeltech_6.5/myproject/11-01.Example/environment.sv(86): (vlog-7027) Hierarchical reference ('top.squat.lut.read') not allowed from within a package.
    ** Error: utopia.sv(69): near "interface": syntax error, unexpected "interface", expecting "assert "
    后来我想既然不是 Auto-Generating Compile Order的问题，那可能就是源文件应该有特定的编译顺序，可是不管怎么调整编译顺序，编译以后还是会出现error。
    我实在是不知道应该怎么解决了，希望你能再帮我看一下，非常感谢。