ISE编译，出现警告“WARNING:Xst:1467...."原因

thereywb · 发表于 2014-10-6 17:26:22

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我是新手。结合网上资料，我用ISE写了一个SPI控制接口，其中接收数据代码如下：

module spi_receive_module(
input clk,
input rst,
input mosi,
input cs,
input sck_p,
output reg rxc_flag,
output reg [7:0]rx_data
);
reg[1:0] rx_state;
reg[7:0] byte_receive;
reg[2:0] bit_re_cnt;
reg[2:0] rxc_flag_width;
always@(posedge clk or negedge rst or posedge cs)
begin
if(!rst)
begin
rxc_flag<=1'b0;
rx_data<=8'd0;
rx_state<=2'b00;
bit_re_cnt<=3'b000;
rxc_flag_width<=3'b000;
end
else if(cs)
begin
rx_state<=2'b00;
bit_re_cnt<=3'd0;
end
else begin
case(rx_state)
2'b00:begin
//byte_receive={byte_receive[6:0],mosi};
if(sck_p && !cs)
begin
byte_receive={byte_receive[6:0],mosi};
rxc_flag<=1'b0;
if(bit_re_cnt==3'd7)
begin
bit_re_cnt<=3'd0;
rx_state<=2'b01;
rxc_flag<=1'b1;
end
else
begin
bit_re_cnt<=bit_re_cnt+1'b1;
end
end
else
begin
rx_state<=2'b00;
end
end
2'b01:begin
rx_data<=byte_receive;
//rxc_flag<=1'b1;
if(rxc_flag_width==3'b100)
begin
rxc_flag_width<=3'b000;
rx_state<=2'b10;
end
else
begin
rxc_flag_width<=rxc_flag_width+1'b1;
end
end
2'b10:begin
rxc_flag<=1'b0;
rx_state<=2'b00;
end
default:rx_state<=2'b00;
endcase
end
end
endmodule

复制代码

编译时出现如下警告：
WARNING:Xst:1467 - "spi_receive_module.v" line 56: Reset or set value is not constant in <byte_receive>. It could involve simulation mismatches
WARNING:Xst:1467 - "spi_receive_module.v" line 56: Reset or set value is not constant in <byte_receive>. It could involve simulation mismatches
WARNING:Xst:1467 - "spi_receive_module.v" line 41: Reset or set value is not constant in <rxc_flag>. It could involve simulation mismatches
WARNING:Xst:1467 - "spi_receive_module.v" line 42: Reset or set value is not constant in <rx_data>. It could involve simulation mismatches
WARNING:Xst:1467 - "spi_receive_module.v" line 45: Reset or set value is not constant in <rxc_flag_width>. It could involve simulation mismatches

请各位前辈指点一二，小弟非常感谢

thereywb · 发表于 2014-10-6 20:49:30

我将敏感信号negedge rst or posedge cs 去掉警告消失了，但是原因我不是太清楚，希望对遇到相似情况的网友有所帮助，同时也希望得到高手们的指教

anovickis · 发表于 2014-10-7 00:52:56

posedge clk or negedge rst or posedge cs

no such flip flop, please rework to use only posedge xx, or negedge xx - not both

thereywb · 发表于 2014-10-7 09:30:09

回复 3# anovickis

谢谢你的提醒，我看过的例程中的确也没有这种写法！

zhangbinsniper · 发表于 2014-10-7 10:13:18

The signal "CS" should be level controling signal. So I personally think it is not suitable to use edge to trigger series operation.

成长中的原始人 · 发表于 2014-10-8 11:08:02

(posedge clk or negedge rst) 可以这样写

奋斗的小熊 · 发表于 2014-10-8 15:12:48

每个case中的信号赋值不全吧

thereywb · 发表于 2014-10-8 18:43:25

回复 6# 成长中的原始人
嗯，加三个触发信号就会有警告，功能仿真没问题，但是程序烧到板子里就有问题（没信号）

shashabiaoge · 发表于 2014-10-20 11:52:34

这样写always(posedge clk or negedge rstn),三个敏感变量时compile没有对应的寄存器

[求助] ISE编译，出现警告“WARNING:Xst:1467...."原因

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