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发表于 2014-4-25 06:14:44
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As I said earlier, there are lots of options for this design. Your clock speed is very slow, and I believe you can use an integrator approach. Here are some hints for you:
1. Let's assume your clock cycle is T;
2. You wanna check if the duty cycle is great than 30%;
3. So tH=0.3T, tL=0.7T;
4. Now let's build a circuitry that is similar to PLL charge pump with a source current isource, and a sink current isink;
5. If we use this charge pump to charge/discharge a capacitor, the charge difference is Qdiff = isource * tH - isink * tL;
6. OK, let's tweak isource and isink, and make isource = 7i and isink = 3i;
7. Then Qdiff = 7i * 0.3T - 3i * 0.7T = 0 if duty cycle is exactly 30%;
8. So if you monitor Vout at the capacitor (Qdiff = Vdiff * C) for some periods, for example, 20, 30 or 100 cycles, you'll be able to get a very accurate result.
Of course, you need to design the circuit carefully, such as minimizing the mismatch between isource & isink. And be aware of clock feedthrough, charge injection and etc. |
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