RTL Design Style Guide for Verilog HDL

dreamfly123123 · 发表于 2018-5-2 10:25:21

昨天下载的找不到了

dreamfly123123 · 发表于 2018-5-2 10:27:47

准备做成中文

jimcmwang · 发表于 2018-5-7 13:07:46

RTL Design Style Guide for Verilog HDL.pdf (7.12 MB)

jimcmwang · 发表于 2018-5-7 13:09:13

RTL Design Style Guide for Verilog HDL.pdf (7.12 MB)

gubels · 发表于 2018-5-22 13:16:41

Reply 1# winever

Frontendsomeexamplesplease

tpungi · 发表于 2018-9-7 20:17:57

thanks you for sharing

yyaoecit2018 · 发表于 2018-9-8 04:29:25

硬骨头，果断要啃！感谢分享！

chungchan · 发表于 2018-10-7 16:51:39

Good share. Looking for a book on ASIC RTL design

rrww · 发表于 2018-10-27 10:46:14

fdsfdsfds

lxyx · 发表于 2018-10-29 12:14:02

参考下，谢谢分享

[资料] RTL Design Style Guide for Verilog HDL