关于一个基准电压的求助

jiang_shuguo

is there any strict limit of area ? maybe the area is the cost.

jiang_shuguo

you also need to  check the output resistance of bandgap vs fre ,and how to figure it

jiang_shuguo

you only give the dc output resistance of bandgap ,and it is useless.

jiang_shuguo

if u have  depletion nmos available ,the ripple of power is to be unvisibility by another solution

whb610

回复 22# jiang_shuguo


   我在bandgap输出端加5u：5u m=100的nmos电容仿真了一下PSRR，在10Hz以下，60db，35M以上，34db，10Hz~35MHz之间最小20db，中频的电源抑制很不满意啊，高频电源抑制也小了一点；也加纹波仿了一下瞬态，高频时bandgap输出端纹波大概在10mV的幅度，比我预想的要好，但是幅度还是太大大，这个在实测恐怕要超过2%，并且在数字电路的干扰下很难说实际应用中没有中频纹波；   输出电阻不能更小了，原因就在于低功耗，我给你的输出电阻值就是bandgap的输出支路上输出对地的电阻，对电源是pmos的电流源，这个可以认为阻值远大于对地电阻，忽略了；我要降低输出电阻值就只能增加整个bandgap的功耗

jiang_shuguo

you need special care about the pst of medium fre .there also need a R before nmos cap ,but this R will affect you psr worst and trans result better. the output restance of bandgap is the whole of bandgap system not one branch.you leave the bandgap loop behand you head!

jiang_shuguo

So now we ture our mind ,Do  u have depletion nmos? i guess u have(process of soc chip always take depletion nmos available.)

jiang_shuguo

So now we turn our mind ,Do  u have depletion nmos? i guess u have(process of soc chip always take depletion nmos available.)
sorry about some spelling mistake!

whb610

回复 24# jiang_shuguo


   没耗尽型NMOS   你是指用耗尽型NMOS做驱动管，D端接VDD，G端接对VDD进行RC滤波的控制信号，S端作为整个电路供电电源，来达到高电源抑制比的目的，是这意思吗

jiang_shuguo

almost it.