关于verilog的问题，求大神解答

swis

我要写一个简单的电梯控制verilog。我想问问这样写有什么问题吗？谢谢。


module semester(
  input  [3:0]w,
  input Clock,
  input switch,
    output  first,
    output  second,
    output  third,
    output  fourth
    );
  reg [2:0] y;
  reg [1:0] counter;
  initial begin
  counter=00;
  y=001;
  end
  parameter [2:0] A = 3'b000, B = 3'b001, C = 3'b010, D= 3'b011,E=3'b100,F=3'b101,G=3'b110,H=3'b111;
always@ (posedge Clock)begin
case (y)
A:
  if(w==0001|switch==1) begin
   y<=A;
   counter=00;
  end
  else if(!counter==11&(w==0000|w==0010|w==0100|w==1000)&switch==0)
   counter=counter+1;
  else if(counter==11&(w==0000|w==0010|w==0100|w==1000)&switch==0) begin
   y<=B;
   counter=00;
  end
B:
  if(w==0000)
   y<=B;
  else if(w==0001)
   y<=A;
  else if((w==0010|w==0100|w==1000)&!counter==01)
   counter=counter+1;
  else if((w==0010|w==0100|w==1000)&counter==01) begin
   y<=D;
   counter=00;
   end
C:
  if(w==0010|switch==1) begin
   y<=C;
   counter=00;
  end
  else if((w==0000|w==0001|w==0100|w==1000)&!counter==11&switch==0)
   counter=counter+1;
  else if((w==0000|w==0001|w==0100|w==1000)&counter==11&switch==0)begin
   y<=D;
   counter=00;
  end

D:
  if(w==0000)
   y<=D;
  else if(w==0010)
   y<=C;
  else if((w==0001|w==0100|w==1000)&!counter==01)
   counter=counter+1;
  else if(w==0001&counter==01) begin
   y<=B;
   counter=00;
  end
  else if((w==0100|w==1000)&counter==01) begin
   y<=F;
   counter=00;
  end

  
E:
  if(w==0100|switch==1) begin
   y<=E;
   counter=00;
  end
  else if((w==0000|w==0001|w==0010|w==0100)&!counter==11&switch==0)
   counter=counter+1;
  else if((w==0000|w==0001|w==0010|w==0100)&counter==11&switch==0)begin
   y<=F;
   counter=00;
  end

F:
  if(w==0000)
   y<=F;
  else if(w==0100)
   y<=E;
  else if((w==001|w==0010|w==1000)&!counter==01)
   counter=counter+1;
  else if((w==0001|w==0010)&counter==01) begin
   y<=D;
   counter=00;
  end
  else if(w==1000&counter==01) begin
   y<=H;
   counter=00;
   end
G:
  if(w==1000|switch==1) begin
   y<=G;
   counter=00;
  end
  else if((w==0000|w==0001|w==0010|w==0100)&!counter==11&switch==0)
   counter=counter+1;
  else if((w==0000|w==0001|w==0010|w==0100)&counter==11&switch==0) begin
   y<=H;
   counter=00;
  end


H:
  if(w==0000)
   y<=H;
  else if(w==1000)
   y<=G;
  else if((w==0001|w==0010|w==0100)&!counter==01)
   counter=counter+1;
  else if((w==0001|w==0010|w==0100)&!counter==01) begin
   y<=F;
   counter=00;
   end
  default y<=3'bxxx;
endcase
end
assign first=~y[0]&~y[1]&~y[2];
assign second=!y[0]&y[1]&!y[2];
assign third=!y[0]&!y[1]&y[2];
assign fourth=!y[0]&y[1]&y[2];
endmodule

sonson2008

大概看了下
这个只能仿真吧。。initial 这种不能综合吧
W==0010这种要写成显式。比如W= 4'b0010
default后面加冒号。
阻塞和非阻塞赋值不要弄在一个always里面

swis

回复 2# sonson2008


    非常感谢。

504472832

回复 3# swis


    可以考虑加根复位信号，然后把initial里的东西扔里面

adamsogood

四层楼，为什么用八个状态？

另外，这是什么意思？
else if(!counter==11&(w==0000|w==0010|w==0100|w==1000)&switch==0)

!counter==11 什么意思？ do you mean (count!=2'b11)？？？

这样写，太难读了。。。