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要求对以下场景做assertion:
如果a 脉冲后要来c脉冲,则中间必须有个b脉冲。
自己写了一个,但是感觉不是很好。同时只能在vcs下编译通过,irun会有语法错误。想看看有没有更好的写法。谢谢大家。
- module a ( ); reg a , b ,c; reg clk; initial begin init_var;
- delay(1);
- //success a=1; delay(2); a = 0; delay(10);
- a=1; delay(2); a = 0; delay(10);
- b=1; delay(2); b = 0; delay(10);
- c=1; delay(2); c = 0; delay(10);
- //failed a=1; delay(2); a = 0; delay(10);
- a=1; delay(2); a = 0; delay(10);
- c=1; delay(2); c = 0; delay(10);
- $finish(); end
- sequence seq_rd_to_wr(a,b); !a[*1:$] ##1 $rose(b); endsequence
- sequence rose_wr(a,b,c); //@(posedge clk) $fell(a) ##1 !a[*1:$] ##1 $rose(b) ##[1:$] $rose(c); s_rd(a) intersect s_cs(b,c); endsequence
- sequence s_rd(a); @(posedge clk) $fell(a) ##1 !a[*1:$]; endsequence
- sequence s_cs(b,c); @(posedge clk) !b[*1:$]##1 b[*2] ##1 !b[*1:$] ##1 $rose(c); endsequence
- property prop_check_rd_to_wr; @(posedge clk) $rose(c) |-> rose_wr(a,b,c).triggered; endproperty
- A_check_rd_to_wr:assert property(prop_check_rd_to_wr);
- parameter PERIOD = 20; always begin #(PERIOD/2) clk = ~clk; end
- task init_var(); begin a <= 0 ; b <= 0 ; c <= 0 ; clk <= 0; end endtask
- task delay(int clk_num=1); #(clk_num*PERIOD); endtask task automatic pulse(int clk_num=1,ref i); i = 1; repeat(clk_num) @(posedge clk); i = 0; endtask
- initial begin:fsdb_block $fsdbAutoSwitchDumpfile(100,"a.fsdb",100); $fsdbDumpvars(0,"a","+all"); endendmodule
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