【关于AMBA AXI 总线的专题讨论】

timing74

从你贴的这个图来看你的三个问题：
1. AHB这边的起始地址是0x0A, A是1100,而AXI这边要求最低三位地址都为0，所以是未对齐的访问。
2. 箭头的起始地方我觉得也有问题，感觉用WLAST组合WREADY应该比较安全。如果用WVALID来判断，SLAVE为一周期响应也可以。
3.这两个地址是算出来的。0x0A包含在0x08起始的地址空间中。

裴静

谢谢，我现在已经不看文档了，感觉有很多问题，我现在直接做了一个axi slave 来仿真，看这个adapter到底是什么行为。

裴静

最近有时间，修改了我的axi slave实现，感觉不错。

裴静

timing，还有没有再来？

jackzhang

这个帖子讨论延续了快一年了，不容易，现在加为精华帖。

老扁

我们回到裴静的第一个问题上来，讨论一下atomic的作用吧。
比如exclusive在什么情况下可以发挥自己的作用？

microbear

Start_Address The start address issued by the master.
Number_Bytes The maximum number of bytes in each data transfer.
Data_Bus_Bytes The number of byte lanes in the data bus.
Aligned_Address The aligned version of the start address.
Burst_Length The total number of data transfers within a burst.
Address_N The address of transfer N within a burst. N is an integer from 2-16.
Wrap_Boundary The lowest address within a wrapping burst.
Lower_Byte_Lane The byte lane of the lowest addressed byte of a transfer.
Upper_Byte_Lane The byte lane of the highest addressed byte of a transfer.
INT(x) The rounded-down integer value of x.
Use these equations to determine addresses of transfers within a burst:
• Start_Address = ADDR
• Number_Bytes = 2SIZE
• Burst_Length = LEN + 1
• Aligned_Address = (INT(Start_Address / Number_Bytes) ) x Number_Bytes.
Use this equation to determine the address of the first transfer in a burst:
• Address_1 = Start_Address.
Use this equation to determine the address of any transfer after the first transfer in a
burst:
• Address_N = Aligned_Address + (N – 1) x Number_Bytes.
For wrapping bursts, the Wrap_Boundary variable is extended to account for the wrapping
boundary:
• Wrap_Boundary = (INT(Start_Address / (Number_Bytes x Burst_Length)))
x (Number_Bytes x Burst_Length).
If Address_N = Wrap_Boundary + (Number_Bytes x Burst_Length), use this equation:
• Address_N = Wrap_Boundary.

Use these equations to determine which byte lanes to use for the first transfer in a burst:
• Lower_Byte_Lane = Start_Address - (INT(Start_Address / Data_Bus_Bytes))
x Data_Bus_Bytes
• Upper_Byte_Lane = Aligned_Address + (Number_Bytes - 1) -
(INT(Start_Address / Data_Bus_Bytes)) x Data_Bus_Bytes.
Use these equations to determine which byte lanes to use for all transfers after the first
transfer in a burst:
• Lower_Byte_Lane = Address_N – (INT(Address_N / Data_Bus_Bytes))
x Data_Bus_Bytes
• Upper_Byte_Lane = Lower_Byte_Lane + Number_Bytes – 1.
Data is transferred on:
• DATA[(8xUpper_Byte_Lane) + 7 : (8 x Lower_Byte_Lane)].

microbear

The exclusive access mechanism enables the implementation of semaphore type
operations without requiring the bus to remain locked to a particular master for the
duration of the operation. The advantage of exclusive access is that semaphore type
operations do not impact either the critical bus access latency or the maximum
achievable bandwidth.

老扁

原帖由 microbear 于 2006-8-15 12:34 发表
The advantage of exclusive access is that semaphore type
operations do not impact either the critical bus access latency or the maximum
achievable bandwidth.

spec上就写了这一句，具体的优点在系统设计里如何体现，如何理解，大家可以一起讨论一下。

microbear

The basic process for an exclusive access is:
1. A master performs an exclusive read from an address location.
2. At some later time, the master attempts to complete the exclusive operation by
performing an exclusive write to the same address location.
3. The exclusive write access of the master is signalled as:
• Successful if no other master has written to that location between the read
and write accesses.
• Failed if another master has written to that location between the read and
write accesses. In this case the address location is not updated.
Note
A master might not complete the write portion of an exclusive operation. The
exclusive access monitoring hardware must monitor only one address per
transaction ID. Therefore, if a master does not complete the write portion of an
exclusive operation, a subsequent exclusive read changes the address that is being
monitored for exclusivity.

Locked accesses require that the interconnect prevents any other transactions occurring
while the locked sequence is in progress and can therefore have an impact on the
interconnect performance. It is recommended that locked accesses are only used to
support legacy devices.