出现警告没法找不到原因

piscesfate · 发表于 2013-5-21 20:55:23

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module decoder
(
num, num_seg
);
input[3:0] num;
output[7:0] num_seg;
reg[7:0] num_seg;
always @(num)
begin
case(num[3:0])
4'd0 : num_seg = 8'b1100_0000;
4'd1 : num_seg = 8'b1111_1001;
4'd2 : num_seg = 8'b1010_0100;
4'd3 : num_seg = 8'b1011_0000;
4'd4 : num_seg = 8'b1001_1001;
4'd5 : num_seg = 8'b1001_0010;
4'd6 : num_seg = 8'b1000_0010;
4'd7 : num_seg = 8'b1111_1000;
4'd8 : num_seg = 8'b1000_0000;
4'd9 : num_seg = 8'b1001_0000;
endcase
end
endmodule

Warning (10240): Verilog HDL Always Construct warning at decoder.v(10): inferring latch(es) for variable "num_seg", which holds its previous value in one or more paths through the always construct

Warning: Latch decoder:u3|num_seg[0] has unsafe behavior

运行是没有问题，就是会有这个警告，有没有遇到过这个问题的朋友呢