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[IC经典图书系列]《Navabi_verilog_digital_systems_design.pdf》-part8,9

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发表于 2006-7-14 20:15:05 | 显示全部楼层 |阅读模式

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《verilog_digital_systems_design 》

by Zainalabedin Navabi

Northeastern University
University of Tehran

Copyright © 1999 by The McGraw-Hill Companies, Inc. All rights reserved. Manufactured in the United States of America. Except as permitted under the United States Copyright Act of 1976, no part of this publication may be reproduced or distributed in any form or by any means, or stored in a database or retrieval system, without the prior written permission of the publisher.

               
                007-137304-7               
               
        
The material in this eBook also appears in the print version of this title: 0-07-047164-9


All trademarks are trademarks of their respective owners. Rather than put a trademark symbol after every occurrence of a trademarked name, we use names in an editorial fashion only, and to the benefit of the trademark owner, with no intention of infringement of the trademark. Where such designations appear in this book, they have been printed with initial caps.


McGraw-Hill eBooks are available at special quantity discounts to use as premiums and sales promotions, or for use in corporate training programs. For more information, please contact George Hoare, Special Sales, at george_hoare@mcgraw-hill.com or (212) 904-4069.

JavaScript support is required on the netLibrary site. Table of Contents
§         
Verilog Digital System Design
§         
Contents
§         
Preface
§         
Overview of the Chapters
§         
Suggested Reading Flow
§         
Code Examples
§         
Acknowledgments
§         
Chapter 1— Hardware Design Environments
§         
Chapter 2— Verilog HDL Background
§         
Chapter 3— Design Methodology Based on Verilog
§         
Chapter 4— Basic Concepts in Verilog
§         
Chapter 5— Structural Specification of Hardware
§         
Chapter 6— Design Organization and Parametrization
§         
Chapter 7— Utilities for High-Level Descriptions
§         
Chapter 8— Dataflow Descriptions in Verilog
§         
Chapter 9— Behavioral Description of Hardware
§         
Chapter 10— CPU Modeling for Discrete Design
§         
Chapter 11— Interface Design and Modeling
§         
Appendix A— Frequently Used System Tasks and Functions
§         
Appendix B— Compiler Directives
§         
Appendix C— Verilog HDL Syntax
§         
Appendix D— Parwan Verilog Descriptions
§         
Appendix E— Verilog Synthesis Examples
§         
Appendix F— Software Accompanying This Book
§         
Index
§         
About the Author

[ 本帖最后由 vertyang 于 2006-7-14 20:22 编辑 ]

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part8

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part9

发表于 2007-4-25 21:56:07 | 显示全部楼层
xiexielouzhu!!!!!!!
发表于 2007-5-12 22:06:25 | 显示全部楼层
感谢楼主啊
发表于 2007-5-14 12:33:04 | 显示全部楼层
xiexielouzhu
发表于 2007-5-15 11:46:56 | 显示全部楼层
怎么没有其他部分,不能解压啊.我现在已经down了1-9了.啊..........
发表于 2007-5-15 11:56:16 | 显示全部楼层
感谢!!!!!!!!!!
 楼主| 发表于 2007-5-24 16:46:00 | 显示全部楼层
各位朋友,实在对不起哈,由于学校网络速度越来越慢,导致后面的部分难以上传。
我决定到网吧给大家传上来,一定会让大家下完的。就在这一两天吧。

请大家到此帖子下载,见谅!
http://www.eetop.cn/bbs/thread-58287-1-1.html

[ 本帖最后由 vertyang 于 2007-5-24 21:24 编辑 ]
发表于 2007-5-24 20:34:05 | 显示全部楼层
谢谢了哦
呵呵
发表于 2009-3-23 22:08:33 | 显示全部楼层
eetop分好多啊
发表于 2013-1-30 09:35:48 | 显示全部楼层
经典好书 不容错过
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