请教： systematic input offset voltage

icdane

请教一下：systematic input offset voltage是怎么产生的？ 一般是在什么电路设计中需要考虑这个问题？ 对电路的影响是什么？ 谢谢！

qerqing

主要受电压增益，阈值和过载的影响吧，至于在什么场合下要注意，那就要看你的电路用途了，一般来说，bjt的电压失调要小可以做到0.1至2mv,，mos的1至20mv，当然也可以采用偏置微调技术或其它一些技术降低失调，这是小弟的认识，欢迎各位大侠指正

hi_china59

Systematic Offset Voltage

The output voltage is nonzero because of mismatches in the input stage, called random offsets, and because the potential on the output of the second stage is not well defined, leading to a systematic offset which can be minimized by careful design.
It does not occur in BJT op amps because of the large gain per stage.
To see how systematic offset can occur, consider the circuit of Fig 5.4 with the differential input voltage is zero (i.e., when Vin+=Vin-).
If the input stage in perfectly balanced, then the voltage appearing at the drain of Q4 (Vds4) will be equal to that at the drain of Q3 (Vds3=Vgs3=Vgs4).
Now this is also the voltage that is fed to gate of Q7 (Vgs7).
In other words, a voltage equal to Vgs4 appears between gate and source of Q7 (Vgs7).
Thus the drain current of Q7, ID7 will be related to the drain current of Q4, which is equal to I, by the relationship

For more detailed inforation, please open the attached pdf file.

sarahsarah

下了，谢谢

sspa

谢谢分享

clare014201

正困惑呢，谢谢答疑！

limpidyou

thanks for this sharing~
I really want to know this!

gggsilicon

高人遍地都是。。。。

abc_whatever

thanks for sharing

leonken440

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