请教DAC SFDR仿真方法

cetband6

请问如何仿真DAC的SFDR特性，对瞬态输出信号做DFT运算时采样点数有什么要求吗，哪位高手帮帮忙。

azo0629

oversampling要做, 因為你想看的是continuous的analog signal

cetband6

请问在一个信号周期内的采样点数应该是等于Fsample/Fout，还是采样点数越大SFDR越正确

cetband6

目前没有

JTR6907

我也不知道诶，学习。。。。。。。

fangdasheng

学习学习，我也不知

winsonpku

采样点数就等于Fsam/Fout

原帖由 cetband6 于 2008-6-15 15:12 发表

                               
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请问在一个信号周期内的采样点数应该是等于Fsample/Fout，还是采样点数越大SFDR越正确

ronialeonheart

一个信号周期内的采样点数就是等于Fsample/Fout
lz想问的应该是：是不是仿真的点数越多，SFDR就越正确
这个说法不完全正确 在仿真的点数小于一个信号周期的采样点数 仿的越多 SFDR越正确
如果在仿真的点数大于一个信号周期的采样点数 仿的越多 SFDR也还是和仿真的点数等于一个信号周期的采样点数的时候一样
因为信息量是一样的

纯白雾隐

请问采样点数一般采多少点？怎么确定？还有那个Fsample要怎么确定？

prof3

SFDR simulation for ADC or DAC is a little bit different. Correctly predict SFDR for  DAC must follow
(1) Proper # of Pts in FFT and your simulation, basically, you need odd number of cycle of signal and have to keep 2^N ppt FFT. E.g. 10bit DAC, best case is to use 1024 pt. Depending on simulation time, most of case 256 pt  can also give us good SDFR prediction.

I don't agree above author said that increasing # of cycle have no use. This is because your cycle repeating. If cohence sampling cycle, definitely helps.

(2) Pls take out the unsettling or overshoot point during the transient simulation. That is to say, you must use true settling points for FFT. Otherwise your SDFR is harm.


Hopefully it helps