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发表于 2022-3-5 17:56:02
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Initializing Memories and Regs
VCS has compile-time options for initializing all bits of memories and regs to the 0, 1, X, or Z value:
+vcs+initmem+0|1|x|z
Initializes all bits of all memories in the design.
+vcs+initreg+0|1|x|z
Initializes all bits of all regs in the design.
The +vcs+initmem option initializes regular memories and multi-dimensional arrays of the reg data type with more than two dimensions, for example:
reg [7:0] mem [7:0][15:0];
The +vcs+initmem option does not initialize multi-dimensional arrays of any other data type.
The +vcs+initreg option does not initialize registers (variables) other than the reg data type.
When you use these options, to prevent race conditions, you should avoid the following :
•Assigning initial values to a regs in their declaration when the value assigned is not the same as the value specified with the +vcs+initreg option, for example:
reg [7:0] r1 8’b01010101;
•Assigning values to regs or memory elements at simulation time 0 when the value assigned is not the same as the value specified with the +vcs+initreg or +vcs+initmem option, for example:
initial
begin
mem[1][1]=8’b00000001;
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