求书《RTL Modeling with SystemVerilog For Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design》

puxiancheng

RTL Modeling with SystemVerilog For Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design
by Stuart Sutherland
Paperback, 488 pages
Copyright 2017, Sutherland HDL, Inc., Tualatin, Oregon
ISBN: 978-1-5467-7634-5

This book is both a tutorial and a reference for engineers who use the SystemVerilog Hardware Description Language (HDL) to design ASICs and FPGAs. The book shows how to write SystemVerilog models at the Register Transfer Level (RTL) that simulate and synthesize correctly, with a focus on proper coding styles and best practices. SystemVerilog is the latest generation of the original Verilog language, and adds many important capabilities to efficiently and more accurately model increasingly complex designs. This book reflects the SystemVerilog-2012/2017 standards. This book is for engineers who already know, or who are learning, digital design engineering. The book does not present digital design theory; it shows how to apply that theory to write RTL models that simulate and synthesize correctly.

yesbird

check it

puxiancheng

打捞一下。。。

loveineda

我从美亚买了原版书，好像没有电子版吧

此书写得是非常清晰，不愧为IEEE1800制定者写的书，

不过太基础了，最最基本的，

我愿意把我的书卖给你

puxiancheng

loveineda 发表于 2019-8-2 16:05
我从美亚买了原版书，好像没有电子版吧

此书写得是非常清晰，不愧为IEEE1800制定者写的书，

非常感谢。恩，我看到亚马逊有卖。就是不想倒腾纸质书

yeda

where is the pdf ?

ever4ever

楼主找到了么？

zhaowentao

同求呀~

darrenjing

我也找了很久了，他要是有pdf卖我就买了

jacobshen

puxiancheng 发表于 2019-8-2 18:56
非常感谢。恩，我看到亚马逊有卖。就是不想倒腾纸质书

用软件扫描一下