systemverilog uvm 1.2 workshop user guide & lab guide

changli74 · 发表于 2018-7-20 04:05:11

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本帖最后由 changli74 于 2018-7-20 12:40 编辑

In this hands-on workshop, you will learn how to develop a UVM 1.1 and UVM 1.2 SystemVerilog testbench environment which enables efficient testcase development. Within the UVM environment, you will develop stimulus sequencer, driver, monitor, scoreboard and functional coverage. Once the UVM environment has been created, you will learn how to easily manage and modify the environment for individual testcases.
You will learn how to use the configuration database to control both, component behavior and stimulus generation. You will use the power of Object-oriented programming to easily replace component and transaction objects with their derived-class variations. You will learn how to use callbacks to increase the controllability and observability of the testbench. You will also learn how to model registers in UVM that simplify the configuring and testing the registers in your device.

Synopsys_uvm1.2_lab_guide.pdf (12.53 MB, 下载次数: 1580 )

synopsys sv uvm1.2.part1.rar (14 MB, 下载次数: 1518 )

synopsys sv uvm1.2.part3.rar (11.01 MB, 下载次数: 1363 )

yuanpin318 · 发表于 2018-7-20 09:36:53

Where is it?

student321 · 发表于 2018-7-20 21:14:04

:victory::victory::victory:

复制代码

apteye · 发表于 2018-7-21 12:42:19

thanks.goodtext

tu_yjq123 · 发表于 2018-7-22 23:10:54

多谢分享

lhyi · 发表于 2018-7-23 06:09:23

very nice, thank you

mailtoanoopbabu · 发表于 2018-7-23 10:03:11

thakksjlf

anykatest · 发表于 2018-7-23 11:04:22

thx ，good ；123

yuanpin318 · 发表于 2018-7-23 20:45:46

终于找到了

差一颗米 · 发表于 2018-7-24 09:17:20

非常感谢

[资料] systemverilog uvm 1.2 workshop user guide & lab guide

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