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ISE或modelsim的行为仿真时序图:
vivado2014/vivado2016的行为仿真时序图:
counter源码:
- `timescale 1ns / 1ps
- module counter(
- input clk,
- input rst,
- input enable,
- output [7:0] count
- );
- reg [7:0] count_r;
- assign count = count_r;
- always@(posedge clk)
- if(rst)
- count_r <= 8'd0;
- else begin
- if(enable) begin
- if(count_r < 8'd203)
- count_r <= count_r + 1'b1;
- else
- count_r <= 8'd0;
- end
- end
- endmodule
复制代码
techbench源码:
- module counter_tb();
- reg clk;
- reg reset;
- reg enable;
- wire [7:0] count;
- counter uut (
- .clk(clk),
- .rst(reset),
- .enable(enable),
- .count(count)
- );
- initial begin
- // Initialize Inputs
- clk = 0;
- reset = 1;
- enable = 0;
- // Wait 100 ns for global reset to finish
- #100;
- reset = 0;
- @(posedge clk);
- @(posedge clk);
- @(posedge clk);
- @(posedge clk);
- @(posedge clk);
- @(posedge clk);
- @(posedge clk);
- enable = 1'b1;
- @(posedge clk);
- @(posedge clk);
- @(posedge clk);
- @(posedge clk);
- enable = 1'b0;
- @(posedge clk);
- @(posedge clk);
- @(posedge clk);
- @(posedge clk);
- enable = 1'b1;
- @(posedge clk);
- @(posedge clk);
- @(posedge clk);
- @(posedge clk);
- #100;
- $finish;
- // Add stimulus here
- end
- always #5 clk = ~clk;
-
- endmodule
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