代码综合出现的错误，请指教

Lydia_yy

我的代码在功能仿真阶段是正确的，而综合时就会出错，请各位指点一下：
代码如下：
module counter(CLK_100M, RST, DIN, CLK_1M, OUT);
    input CLK_100M;
  input DIN;
  input RST;
  output CLK_1M;
  output [7:0]OUT;
  
  reg [5:0]j;
  reg CLK_1M;
  
  reg CNT1_EN;
  reg [7:0]k;
  reg LOCK;
  
  wire CLR;
  
  reg [7:0]Photo_Q1;
  reg [7:0]Photo_Q2;
  
  reg [7:0]OUT;
  
  
//  CLK_1M     division module
   [email=always@(posedge]always@(posedge[/email] CLK_100M)
   if(!RST)
     begin j<=0; CLK_1M<=0; end
   else if(j==49)
              begin  CLK_1M<=~CLK_1M; j<=0; end
           else
              j<=j+1;  
//  EN,LOCK
   always @(posedge CLK_100M)
   if (!RST)
     begin k<=0; CNT1_EN<=0; end
   else if(k==99)
           begin k<=0; CNT1_EN<=~CNT1_EN; LOCK<=1;end
     else
             begin k<=k+1; LOCK<=0;end
   
//  assign CNT2_EN =~CNT1_EN;
            
// CLR
       assign CLR=~LOCK;

//  photo_Q1, photo_Q2      Counter   
  always @(posedge CLK_100M)
     if(!RST)
     begin Photo_Q1 <=0; Photo_Q2 <=0; end
   else if (CNT1_EN)
             if(DIN)
            Photo_Q1 <=Photo_Q1+1;
        else
                      Photo_Q1 <=Photo_Q1;
         else
              if(DIN)
           Photo_Q2 <=Photo_Q2+1;
      else
                       Photo_Q2 <=Photo_Q2;      

// 锁存模块  
  [email=always@(posedge]always@(posedge[/email] LOCK )
    if(!CNT1_EN)
       begin OUT<=Photo_Q1; end
  else
       begin OUT<=Photo_Q2; end   
     
// 清零模块     
   [email=always@(posedge]always@(posedge[/email] CLR)
     if(!CNT1_EN)
     Photo_Q1<=0;
   else
         Photo_Q2<=0;

endmodule


提示error如下：
ERROR:Xst:528 - Multi-source in Unit <counter> on signal <Photo_Q1<7>>
Sources are:
   Output signal of FDRE instance <Photo_Q1_7>
   Signal <Photo_Q1<7>> in Unit <counter> is assigned to GND
ERROR:Xst:528 - Multi-source in Unit <counter> on signal <Photo_Q1<6>>
Sources are:
   Output signal of FDRE instance <Photo_Q1_6>
   Signal <Photo_Q1<6>> in Unit <counter> is assigned to GND
ERROR:Xst:528 - Multi-source in Unit <counter> on signal <Photo_Q1<5>>
Sources are:
   Output signal of FDRE instance <Photo_Q1_5>
   Signal <Photo_Q1<5>> in Unit <counter> is assigned to GND
ERROR:Xst:528 - Multi-source in Unit <counter> on signal <Photo_Q1<4>>
Sources are:
   Output signal of FDRE instance <Photo_Q1_4>
   Signal <Photo_Q1<4>> in Unit <counter> is assigned to GND
ERROR:Xst:528 - Multi-source in Unit <counter> on signal <Photo_Q1<3>>
Sources are:
   Output signal of FDRE instance <Photo_Q1_3>
   Signal <Photo_Q1<3>> in Unit <counter> is assigned to GND
ERROR:Xst:528 - Multi-source in Unit <counter> on signal <Photo_Q1<2>>
Sources are:
   Output signal of FDRE instance <Photo_Q1_2>
   Signal <Photo_Q1<2>> in Unit <counter> is assigned to GND
ERROR:Xst:528 - Multi-source in Unit <counter> on signal <Photo_Q1<1>>
Sources are:
   Output signal of FDRE instance <Photo_Q1_1>
   Signal <Photo_Q1<1>> in Unit <counter> is assigned to GND
ERROR:Xst:528 - Multi-source in Unit <counter> on signal <Photo_Q1<0>>
Sources are:
   Output signal of FDRE instance <Photo_Q1_0>
   Signal <Photo_Q1<0>> in Unit <counter> is assigned to GND

vincent_zy

有信号在多个模块里面赋值了

Lydia_yy

能不能具体一些哪？ 功能仿真是没有错误的；谢

paperfly

也就是说：每个变量不能再多个always语句中被赋值

霡霂

你在计数模块和清零模块里面都对photo_q进行赋值了 把清零模块也放到计数模块里面就可以了

Lydia_yy

I konw了，谢谢楼上的；就是说：同一个reg的赋值不要放到多个always块中。

yuanwolf2008

同一个reg的赋值不要放到多个always块中

MOSFET

3年前的东西都能挖出来~

daidaohan

已经解决了啊

liushihong

说说怎样弄好的？学习一下