在我的设计中,我用了2个DCM,外部时钟通过全局时钟引脚进入FPGA,在FPGA内部,我对时钟信号进行了如下处理,IBUFG+BUFG+DCM(两个),得到了两组频率比较高的时钟信号,这样的设计在不添加chipscope时是没问题的,综合,布线均能通过。但是,添加chipscope,在ILA中,采样时钟设置为时钟信号(这些时钟信号都是全局时钟信号),布线出现了错误“ERRORlace:1138 - Automatic clock placement failed. Please attempt to analyze the global clocking required for this
design and either lock the clock placement or area locate the logic driven by the clocks so that the clocks may be
placed in such a way that all logic driven by them may be routed. The main restriction on clock placement is that
only one clock output signal for any competing Global / Side pair of clocks may enter any region. For further
information see the "Quadrant Clock Routing" section in the Spartan3e Family Datasheet.”
我不知道这是什么原因,是我的时钟树出错了吗?但是为什么在不添加chipscope时不报错;还是我的采样时钟设置出来问题?请论坛上的大神们,能给个建议啊!!