High Speed and Wide Bandwidth Delta-Sigma ADCs

luckyjohn1688

Makinwa 教授的新作
1 Introduction .................................................................. 1
1.1 Trends in Wide Bandwidth and High Dynamic Range ADCs ........ 3
1.2 Motivation and Objectives.............................................. 4
1.3 Organization of the Book ............................................... 5
References ..................................................................... 6
2 Continuous-Time Delta-Sigma Modulator ................................ 9
2.1 Ideal Delta-Sigma Modulator........................................... 9
2.1.1 System Overview ............................................... 9
2.1.2 Quantizer ........................................................ 12
2.1.3 DAC ............................................................. 15
2.1.4 Loop Filter ...................................................... 16
2.2 System-Level Non-idealities ........................................... 19
2.2.1 Noise ............................................................ 20
2.2.2 Non-linearity .................................................... 22
2.2.3 Excess Loop Delay ............................................. 24
2.2.4 Metastability .................................................... 30
2.3 Summary ................................................................ 33
References ..................................................................... 34
3 Continuous-Time Delta-Sigma Modulators at High
Sampling Rates............................................................... 37
3.1 System-Level Design ................................................... 37
3.1.1 CT† Modulator Design at High Sampling Rates........... 37
3.1.2 Excess Loop Delay Compensation with an Active
Amplifier ........................................................ 40
3.1.3 High-Speed Capacitive Feedforward CT † Modulator..... 46
3.2 Block-Level Design Requirements..................................... 50
3.2.1 Loop Filter ...................................................... 51
3.2.2 Quantizer ........................................................ 57
3.2.3 Feedback DAC (DAC1) ........................................ 64
3.2.4 Quantizer DAC (DAC2) ........................................ 68

3.3 Conclusions ............................................................. 70
References ..................................................................... 71
4 A 4 GHz Continuous-Time † ADC ...................................... 73
4.1 Introduction ............................................................. 73
4.2 Implementation Details ................................................. 74
4.2.1 CT† ADC Architecture ...................................... 74
4.2.2 Quantizer Design and Timing Diagram of the Modulator .... 75
4.2.3 Feedback DACs................................................. 78
4.2.4 Operational Transconductance Amplifier...................... 80
4.2.5 Decimation Filter ............................................... 81
4.3 Experimental Results ................................................... 81
4.3.1 Measurement Setup ............................................. 81
4.3.2 Measurement Results ........................................... 82
4.4 Conclusions ............................................................. 92
References ..................................................................... 92
5 A 2 GHz Continuous-Time † ADC with Dynamic Error
Correction .................................................................... 95
5.1 Introduction ............................................................. 95
5.2 Dynamic Error Correction Techniques in † Modulators ........... 100
5.2.1 The Error Switching Technique ................................ 104
5.3 Multi-mode High-Speed † ADC Design ............................ 105
5.4 Implementation Details ................................................. 108
5.4.1 Input Stage and the Loop Filter ................................ 109
5.4.2 Pulse Generator ................................................. 110
5.5 Experimental Results ................................................... 112
5.6 Conclusions ............................................................. 115
References ..................................................................... 115
6 Conclusions ................................................................... 117
6.1 Benchmarking ........................................................... 118
6.2 Future Work ............................................................. 119
References ..................................................................... 121
A Comparison of ADC Architectures ........................................ 123
B Non-linearity of an Ideal Quantizer ....................................... 127
References ..................................................................... 128
Glossary ........................................................................... 129
Index ............................................................................... 131


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High Speed and Wide Bandwidth Delta-Sigma ADCs

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