请大家帮忙看看这段描述同步fifo的代码有问题么？

xz2001cih

module sfifo (clk,rst,rd,wr,data_in,data_out,empty,full)
input clk,rst,rd,wr;
input[7:0] data_in;
output empty,full;
output[7:0] data_out;
reg[7:0] data_out;        //fifo宽度为8bit  
reg[7:0] data_mem[7:0];  //fifo深度为8
reg[2:0] wr_pt,wr_pt;

assign empty=(wr_pt-rd_pt==1)?1'b1:1b'0;
assign full=(rd_pt-wr_pt==1)?1'b1:1b'0;


always @(posedge clk or posedge rst)
begin
if (rst)
  begin
  rd_pt<=3'b000;
  wr_pt<=3'b000;
  end
else
  if (~rd & wr)
  begin
  rd_pt<=rd_pt+1;
  data_out<=data_mem[rd_pt];
  end
  else if (~wr & rd)
  begin
  wr_pt<=wr_pt+1;   data_mem[wr_pt]<=data_in;
  end

  case ({empty,full})
  2'b10 rd_pt<=3'b000;
  2'b01 wr_pt<=3'b000;
end


always @(posedge clk or posedge rst)

begin
if (empty==1)
$print ("\n error");
else if (full==1)
$print ("\n error");
end

endmodule