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本帖最后由 hancheng1166 于 2013-4-2 00:58 编辑
鄙人最近正在研究mips processor.用verilog写,之前一直在用vhdl的,但是最近发现一个问题,下面我贴一下代码
- always @(*)
- begin
- casex({aluop_ex, funct})
- 6'b000??? : alu_ctrl <= 0000;
- 6'b010000 : alu_ctrl <= 0000;
- 6'b010001 : alu_ctrl <= 0001;
- 6'b010010 : alu_ctrl <= 0010;
- 6'b010011 : alu_ctrl <= 0011;
- 6'b010100 : alu_ctrl <= 0100;
- 6'b010101 : alu_ctrl <= 0101;
- 6'b010110 : alu_ctrl <= 0110;
- 6'b010111 : alu_ctrl <= 0111;
- 6'b011000 : alu_ctrl <= 1000;
- 6'b011001 : alu_ctrl <= 1001;
- 6'b100??? : alu_ctrl <= 1010;
- 6'b110??? : alu_ctrl <= 1011;
- 6'b111??? : alu_ctrl <= 1100;
- default : alu_ctrl <= 1111;
- endcase
- end
复制代码
下面是testbench....我在每个延迟10ns的时候控制aluop_ex跟funct的输入的值,就是上面case语句从上到下的值。然后在仿真结果上得到相应的时间也就是alu_ctrl前面的数字,同时得到alu_ctrl的值。
- initial begin
- // Initialize Inputs
- funct = 0;
- aluop_ex = 0;
- #10
- funct = 0;
- aluop_ex = 2;
- #10
- funct = 1;
- aluop_ex = 2;
- #10
- funct = 2;
- aluop_ex = 2;
- #10
- funct = 3;
- aluop_ex = 2;
- #10
- funct = 4;
- aluop_ex = 2;
- #10
- funct = 5;
- aluop_ex = 2;
- #10
- funct = 6;
- aluop_ex = 2;
- #10
- funct = 7;
- aluop_ex = 2;
- #10
- funct = 0;
- aluop_ex = 3;
- #10
- funct = 3;
- aluop_ex = 4;
- #10
- funct = 1;
- aluop_ex = 5;
- #10
- funct = 2;
- aluop_ex = 6;
- #10
- funct = 0;
- aluop_ex = 7;
- // Wait 100 ns for global reset to finish
- #700;
- $stop;
- // Add stimulus here
- end
-
- initial begin
-
- $monitor($time, "alu_ctrl=%b", alu_ctrl);
- end
-
复制代码
下面是结果,我用Isim 仿真的:
- 0alu_ctrl=0000
- 20alu_ctrl=0001
- 30alu_ctrl=1010
- 40alu_ctrl=1011
- 50alu_ctrl=0100
- 60alu_ctrl=0101
- 70alu_ctrl=1110
- 80alu_ctrl=1111
- 90alu_ctrl=1000
- 100alu_ctrl=0010
- 110alu_ctrl=0111
- 120alu_ctrl=0011
- 130alu_ctrl=1100
复制代码
奇怪的结果我用bolder 标识出来了。
但结果应该是:
30alu_ctrl=0010
40alu_ctrl=0011
70alu_ctrl=0110
80alu_ctrl=0111
我用别的simulator 也试过了,比如iverilog结果是一样的。一开始我以为是Bug的问题,但现在觉得可能是我语句哪里有不对的地方、
有知道的大神请指点一下~~
非常感谢~! |
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