Why a rigorous clocking is essential in VLSI?

joemool

我们为什么要做优良的CTS，为什么需要设计缜密的clocking network，以下摘自《Digital Integrated Circuit Design From VLSI Architectures to CMOS Fabrication》：

1. Hazards do not compromise functionality. Clock and asynchronous reset are the only two
signals that must be kept free of hazards under all circumstances. Doing so is easy, strictly
limiting distribution networks to fanout trees suffices.

2. As no timing violations ever occur within a properly designed synchronous circuit, there is no
chance for inconsistent data, marginal triggering, and meta-stability to develop.

3. Immunity to noise and coupling effects is maximum because all nodes are allowed to settle
before any storage operations and state changes occur.


4. All timing constraints are one-sided. For a circuit to function correctly, any timing quantity
is bounded either from above (such as the longest propagation delay, for instance) or from
below (such as the contamination delays). Two-sided constraints do not exist.

5. Together, the four above properties warrant deterministic behavior of circuits independently
from low-level details. Synchronous designs do not rely on delay tuning in any way, what
matters for functional correctness are the data operations at the RTL level exclusively. This
argument cannot be overestimated in view of
• Automatic placement, routing, and physical design verification,
• Automatic HDL synthesis, logic optimization, clock tree generation, and rebuffering,
• Automatic insertion of test structures,
• Reusing a HDL model or a netlist in multiple designs, and
• Retargetting a design from one cell library and/or fabrication process to another (e.g.
from FPL to a mask-programmed IC, or vice versa).

6. A systematic, modular, and efficient approach to design, test, and troubleshooting is impossible
unless history-dependent behavior is strictly confined to clocked storage elements. More
specifically, synchronous operation makes it possible to separate functional verification from
timing analysis and to take advantage of automata theory and related concepts.

7. There is no need for any redundant circuitry to suppress hazards. Standard synthesis tools
are geared towards minimizing circuit complexity while meeting performance constraints; they
are not concerned with transients and their elimination.

8. The operations that are to be carried out in each clock cycle can be stated and collected at
compile time, thereby opening a door for cycle-based simulation techniques that are more
efficient when circuits grow large. Asynchronous circuits, in contrast, are entirely dependent
on event-driven simulation.

9. Established methods for circuit testing (such as fault grading, test vector generation, and
the insertion of test structures) start from the assumption of synchronous operation. What’s
more, almost all test equipment is designed accordingly.

10. Synchronous clocking makes it possible to slow down and even to suspend circuit operation
in any state and for an arbitrary lapse of time, which greatly facilitates the tracing of state
transitions, data transfers, protocol sequences, and computation flow when a malfunctioning
circuit must be debugged. The ability to operate synchronous circuits in speed-limited
environments is often welcome for prototyping purposes.


我想作者已经把他所能想到的都列举出来了，那么我们究竟能对上述10个理由理解多深呢？

请大家开展讨论，仔细思考一下，一定不会浪费你的时间。