FPGA综合时的错误

xidianty

always @(posedge wr_clk or posedge reset)

begin

sche_info_in_dl1<=sche_info_in;

end
这是往模块中写的，sche_info_in是外界的输入，然后往模块中寄存了一下，为什么综合时提示The logic for <sche_info_in_dl1> does not match a known FF or Latch template. The description style you are using to describe a register or latch is not supported in the current software release？？？

pptwo

你的reset信号没有用到，无法综合成一个已知的带异步复位的触发器，建议写成
begin
if (reset)
   sche_info_in_dl1<=0;
else
   sche_info_in_dl1<=sche_info_in;
end

remnant

always @(posedge wr_clk or posedge reset)
begin
    sche_info_in_dl1<=sche_info_in;
end
楼主，请问你能想象出来这是个什么样子的器件吗？

handsomexk

2#正解
或者把异步复位or posedge reset去掉，直接寄存