Dennis Fischette's 1-Stop PLL Center

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[size=+2]Dennis Fischette's 1-Stop PLL Center

http://www.delroy.com/PLL_dir/pll.htm

All questions (with answers) will be posted anonymously unless otherwise requested.
[size=+1]Questions and Answers

How do you estimate accumulated phase error?

References for understanding the noise issues in PLL design?

Could you explain the cycle-skip phenomenon in PLL performance?

Is there a downside of choosing a low bandwidth and big multiplier?

Why does my control voltage oscillate?

Do you have any references to "gate leakage" vs. CMOS process technology?

You've talked about the leakage current (Ileak) for MOS capacitors used in the loop filter. For 130nm process, what is the approximate Ileak?

What are some of the most effective approaches people use to minimize jitter from both design and layout?

What is the best way to simulate the PLL for stability?

Wouldn't the open-loop equation change somewhat for the self-biased PLL based on Maneatis design since there is no actual resistor?

When should I divide the VCO by 2?

What are the effects of dividing the VCO output by 2 on output jitter?

What are the effects of dividing the VCO output by 2 on phase error?

How do you introduce jitter in the simulation?

Since overall the PLL acts like a low-pass filter, doesn't the high-frequency VCO noise mostly get rejected?

If you have questions or suggestions, email me at [url=mailtoLL@delroy.com]PLL@delroy.com[/url]