除法器

njithjw

`timescale 1ns/1ns
module divider
    (
    input               clk,
    input               rst,
    input       [7:0]   dividend,
    input       [7:0]   divisor,
    input               load,

    output  reg [7:0]   ratio,
    output  reg [7:0]   remainder,
    output  reg         finish
    );

reg     [3:0]   cnt;
reg     [16:0]  dividend_widen;
reg     [7:0]   ratio_shift;
wire    [8:0]   sub;
wire    [16:0]  dividend_shift;
always @ (posedge clk or posedge rst)
begin
    if (rst == 1'b1)
        cnt <= 4'd15;
    else if (load == 1'b1)
        cnt <= 4'd0;
    else
        cnt <= cnt + {3'd0,~(&cnt)};
end

always @ (posedge clk or posedge rst)
begin
    if (rst == 1'b1)
        dividend_widen <= 17'd0;
    else if (load == 1'b1)
        dividend_widen <= {9'd0,dividend};
    else
        dividend_widen <= dividend_shift;
end

assign sub = dividend_widen[16:8] - divisor;
assign dividend_shift = (sub[8] == 1'b0)? {sub[7:0],dividend_widen[7:0],1'b0}: {dividend_widen[15:0],1'b0};

always @ (posedge clk or posedge rst)
begin
    if (rst == 1'b1)
        ratio_shift <= 8'd0;
    else
        ratio_shift <= {ratio_shift[6:0],~sub[8]};
end

always @ (posedge clk or posedge rst)
begin
    if (rst == 1'b1)
        ratio <= 8'd0;
    else if (cnt == 4'd9)
        ratio <= ratio_shift;
    else ;
end

always @ (posedge clk or posedge rst)
begin
    if (rst == 1'b1)
        remainder <= 8'd0;
    else if (cnt == 4'd9)
        remainder <= dividend_widen[16:9];
    else ;
end

always @ (posedge clk or posedge rst)
begin
    if (rst == 1'b1)
        finish <= 1'b0;
    else if (cnt == 4'd9)
        finish <= 1'b1;
    else
        finish <= 1'b0;
end

endmodule