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module compare(equal,a,b);
input [2:0] a,b;
output equal;
assign equal=(a==b)?1:0;
endmodule
`timescale 1ns/1ns
`include "compare.v"
module compare_tb;
reg a,b;
initial
begin
a=0;b=0;
#100 a=0;b=1;
#100 a=1;b=1;
#100 a=1;b=0;
#100 $stop;
end
compare compare_tb(equal,a,b);
initial //??????
begin
$monitor("time=%d a=%d b=%d equal=%d",$time,a,b,equal);
end
endmodule
# time= 0 a=0 b=0 equal=x
run
# time= 100 a=0 b=1 equal=0
run
# time= 200 a=1 b=1 equal=x
run
# time= 300 a=1 b=0 equal=0
为什么结果会是这样子啊? |
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