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发表于 2011-5-14 05:03:52
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回复 8# 桦香
hi
Thank you for your reply, and indeed you already provided quite a lot of information. But still without more numbers, it seems hard to detect where the problem really is. My suspects are:
1. In your circuit there are at least three loops, while you only provide bode plot for one, the outer one. There are still two more loops which can cause stability problem, the one with miller cap and the one inside super source follower. Remember there are three prerequsites that PM,GM could be used for stability judgement, and of which the first one is that loop gain itself should be stable. put stb probe inside these loops to check PM.
2. transient induced unstable. As you said Mn24 and Mn25 are off at the beginning of power up, probably due to bootstrap, which might be worse for light load. Other transistor might also not be in proper state like cascode transistor connected to miller cap. If your LDO is used in SOC (instead of general purpose LDO), you might ask for power down and power down delay signal to control you startup sequence properly. |
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