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Abstract
As the logic capacity of field-programmable gate
arrays (FPGAs) increases, they are being increasingly used to
implement large arithmetic-intensive applications. Large arithmetic
intensive applications often contain a large proportion of
datapath circuits. Since datapath circuits are designed to process
multiple-bit-wide data, FPGAs implementing these circuits often
have to transport a large amount of multiple-bit-wide signals from
one computing element (such as a logic block, a DSP block, or
a multi-bit addressable memory cell) to another. In this work,
we investigate the area efficiency of FPGA routing resources
for transporting multiple-bit-wide signals. It is shown that, for
datapath circuits, the switch patterns used by the conventional
routing architecture, which uniformly distribute routing switches
across the routing tracks, are inefficient for connecting the computing
elements to their tracks. The more efficient multi-bit aware
patterns, which contain a densely populated single-bit region and
a sparsely populated multi-bit region, can be effectively used to
reduce the routing area of FPGAs for implementing arithmetic
intensive applications by 6%–10%. It is also shown that the further
sharing of configuration memory among the switches within
the multi-bit aware patterns does not significantly increase their
area efficiency since datapath circuits typically contain a mixture
of multi-bit and single-bit signals—while configuration memory
sharing can substantially increase the area efficiency of routing
resources for transporting multi-bit signals, it also significantly
reduces their ability for transporting single-bit signals. More importantly,
configuration memory sharing can significantly reduce
the effectiveness of the enhanced multi-bit aware patterns—patterns
that incorporate both multi-bit aware and single-bit oriented
switches within a single region in order to increase its ability for
transporting both single-bit and multi-bit signals.
05291700.pdf
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发表于 2011-1-30 11:18:23
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