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[求助] 大家有没有用过CVC, 这个verilog 仿真工具

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发表于 2010-12-30 21:03:03 | 显示全部楼层 |阅读模式

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http://www.pragmatic-c.com/


Pragmatic C Software develops Verilog Hardware Description Language tools. Our flagship product, CVC, is a high performance compiled Verilog HDL simulator. CVC is both flexible enough for initial Verilog logic design and fast enough for server farm regressions using compiled simulation.CVC's high performance and low cost make it the most cost effective Verilog simulator available.
CVC supports the IEEE 1364-2005 Verilog HDL standard. It offers the fastest design elaboration of any Verilog simulator. Its quick elaboration along with its ability to run in interpreted or compiled mode allows for an efficient verification environment.
When performance is critical, CVC compiles Verilog designs making it one of the fastest Verilog simulators on the market. When run in interpreted mode, CVC provides a traditional command line debugger combined with gdb style capabilities.
With IEEE 1364-2005 standard support, CVC is the most cost effective and flexible compiled Verilog simulator on the market. Please visit our productspage for more information or sign up for an evaluation.
发表于 2010-12-31 22:24:29 | 显示全部楼层
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