DC中set_flatten命令的问题

追天鹅的青蛙

最近看书和一些脚本，发现有个脚本在输出网表前，使用set_flatten -effort high 命令，但之后没有编译直接输出网表，感觉有点问题，就做了个实验，测试代码如下，可是不管是否加set_flatten命令编译，结果都是一样的，谁能解答下我的问题，我看了一下资料讲解set_flatten,可是我的实验做不出他们讲的那种效果。

module test(clk,q,d1,d2,d3,d4);

input clk;
input d1,d2,d3,d4;
output q;
reg q;

always @ (posedge clk)
begin
q <=(d1+d2)*d4+d3;
end

endmodule

benjaminweber

flatten是说将有hierarchy的设计打平，去掉层次结构
你的这个代码没有内部子模块，打平与不打平都是一层，当然没区别了

追天鹅的青蛙

回复 2# benjaminweber
ungroup是把层次打平吧，
flatten和structure相对，hierarchy和ungroup相对

benjaminweber

sorry, I am wrong.

雨打溪风

这命令应该很少用到吧

盗墓者

回复 1# 追天鹅的青蛙
Flattening
The goal of this process is to convert combinational logic paths
of the design to a two-level, sum-of-products representation.
Flattening is carried out independently of constraints. It is useful
for speed optimization because it leads to just two levels of
combinational logic.
During flattening, Design Compiler removes all intermediate
variables, and therefore all its associated logic structure, from a
design. Flattening is not always practical, however, because it
requires a large amount of CPU time and can increase area.
By default, Design Compiler does not flatten your design. Use the
set_flatten command to control flattening of your design. The
set_flatten command and its options set the following
attributes: flatten, flatten_effort, flatten_minimize,
and flatten_phase.

speedUp

回复 6# 盗墓者


    这段话是官方的吗？

kuangjianghua

如果把程序中input和output的位宽加几位就有区别了。

DOIC

好像是的，set_flatten ture  和 set_flatten false 的综合后的电路图一样，