本帖最后由 mustangyhz 于 2010-11-27 08:31 编辑
今天看了一个单环、多位量化的sigma delta modulator 的verilog代码，总算大概明白了这个玩意是什么意思，但是还是有几个地方没有看明白，请高手指教
模型
仿真输出
代码 module modulator(clk, rst, k_in, v_out, v_out_offset); input clk, rst; input [23:0] k_in; output [3:0] v_out, v_out_offset; reg [3:0] v_out,v_out_offset; reg [23:0] D1, D2, D3; wire [23:0] sum1, sum2, sum3, sum4, sum5, sum6, sum7, v_fd, v_fd_neg; assign sum1 = k_in + v_fd_neg;减量化输出=加“量化输出”的补码 assign sum2=sum1 + D1; assign sum3=D1 + D2; assign sum4=D2 + D3; assign sum5=D2 + {D2[23],D2[23:1]};1.5倍D2 assign sum6={D1[22:0],D1[0]} + {D3[23],D3[23:1]} +sum5;2倍D1+0.5倍D3+1.5倍D2 assign sum7=sum6[23:19] + 1'b1;取高5位量化，低位去抖 always@(posedge clk or posedge rst) D触发器赋值 begin
if(rst) D1<=24'h0;
else D1<=sum2; end
always@(posedge clk or posedge rst)D触发器赋值 begin
if(rst) D2<=24'h0;
else D2<=sum3; end always@(posedge clk or posedge rst)D触发器赋值 begin
if(rst) D3<=24'h0;
else D3<=sum4; end always@(posedge clk or posedge rst)
begin
if(rst)输出初始化
begin
v_out<=4'b0000;
v_out_offset<=4'b1000;不稳定问题？
end else
begin
v_out<=sum7[4:1];量化结果输出
v_out_offset<=sum7[4:1]+ 4'b1000;加偏移【目的何在？】的量化结果输出
end end assign v_fd=~sum7[4:1]+1'b1;量化结果【5位的高四位】求补码 assign v_fd_neg={v_fd[3:0],20'h00000};低位取反加1在上一行已经实施 endmodule
module test; reg clk; reg rst; reg [23:0] k_dth; reg [31:0] bout_sum, clk_sum, averange; wire [3:0] bout, bout1; modulator M1(clk, rst, k_dth, bout1, bout); always #2 clk = ~clk; initial begin
bout_sum = 25'b0;
clk_sum = 25'b0;
averange = 25'b0;
clk = 1'b0;
k_dth = 24'b0;
rst = 1'b1;
#100000 k_dth = 24'b000000100000000000000000;rst=1'b1;
#1 rst=1'b0;
#100000 k_dth = 24'b000001000000000000000000;rst=1'b1;
#1 rst=1'b0;
#100000 k_dth = 24'b000010000000000000000000;rst=1'b1;
#1 rst=1'b0;
#100000 k_dth = 24'b000010000000001000000000;rst=1'b1;
#1 rst=1'b0;
#100000 k_dth = 24'b000100000000000000000000;rst=1'b1;
#1 rst=1'b0;
#100000 k_dth = 24'b001000000000000000000000;rst=1'b1;
#1 rst=1'b0;
#100000 $stop; end always@(posedge clk or posedge rst) begin
if (rst)
begin
bout_sum = 25'b0;
clk_sum = 25'b0;
averange = 25'b0;
end
else
begin
bout_sum = bout_sum + bout - 8;【减去加的偏移】
clk_sum = clk_sum + 1;
averange = {bout_sum,20'b0}/clk_sum;【补齐了后面的20位】
end endendmodule
代码部分我有两处不明白：
1、assign sum7=sum6[23:19] + 1'b1; 这个应该是取高5位做粗略量化的意思吗？最低位加一是产生伪随机序列的意思吗？好像有篇文章中提过，有详细介绍这个的文章吗？
A 1.1-GHz CMOS Fractional-N Frequency Synthesizer with a 3-b Third-Order SDM：
The fractional division ratio is set to （1/4+1/2(7)）and the 16th bit is used for dithering.【太简单了，看不懂啊：）】
2、 v_out_offset<=4'b1000; v_out_offset<=sum7[4:1]+ 4'b1000;这个我好像是看到一篇文章中提过什么防止边沿不稳定性问题
CMOS Fractional-N Synthesizers Design for High Spectral Purity and Monolithic Integration
. In spite of the stability enhancement an input region for which the modulator becomes unstable exists at
the edges of the input range. Therefore, a 5-bit quantization is applied, by merely isolating the 5
MSBs, although only 4 output bits are needed to control the prescaler moduli. By offsetting the
input by “1000”, the needed 4-bit output range is located in the middle of the total output range.
The resulting output bits are mapped to their 4-bit equivalent by taking only the last 4 of the 5
MSBs {M1, M2, M3, M4} and by inverting Ml, i.e. a subtraction by 8. As can be seen, the unstable input regions are avoided.
谁能帮我详细解释下吗？看得不怎么明白，输入边沿存在不稳定性问题是什么意思？然后和代码中一样，输出前加8【好像对应量化前】，量化后又减8，意义到底何在？
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发表于 2010-11-25 09:02:52
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