如何用Modelsim观察源代码中的中间寄存器信号

tdyizhen1314 · 发表于 2010-6-10 16:22:48

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有谁知道用Modelsim仿真怎么把代码中的中间寄存器信号加进去呢？在激励文件中该怎样修改呀？
比如说用quartus仿真这一点就非常明显  我的意思就是说用modelsim仿真能不能像quartus仿真那样很方便地反寄存器信号加进去呢？
源代码（对时钟进行同步）：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY CLK_TB IS
PORT(CLK_10M: IN STD_LOGIC;
CLK_20M: IN STD_LOGIC;
CLK_50M: IN STD_LOGIC;
DATA_A : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DATA_B : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DATA_OUT: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
DATB_OUT: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
  );
END ENTITY CLK_TB;
ARCHITECTURE ART OF CLK_TB IS
SIGNAL A_1:STD_LOGIC;
SIGNAL A_2:STD_LOGIC;
SIGNAL A_3:STD_LOGIC;
SIGNAL B_1:STD_LOGIC;
SIGNAL B_2:STD_LOGIC;
SIGNAL B_3:STD_LOGIC;
SIGNAL A_OUT:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL B_OUT:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS(CLK_50M,CLK_10M,A_1,A_2,A_3)
BEGIN
  IF CLK_50M'EVENT AND CLK_50M='1' THEN
A_1<=CLK_10M;
A_2<=A_1;
A_3<=(NOT A_2) AND A_1;
  END IF;
END PROCESS;

PROCESS(CLK_50M,CLK_20M,B_1,B_2,B_3)
BEGIN
  IF CLK_50M'EVENT AND CLK_50M='1' THEN
B_1<=CLK_20M;
B_2<=B_1;
B_3<=(NOT B_2) AND B_1;
  END IF;
END PROCESS;

PROCESS(CLK_50M,A_3,DATA_A,A_OUT)
BEGIN
  IF CLK_50M'EVENT AND CLK_50M='1' THEN
IF A_3='1' THEN
A_OUT<=DATA_A;
ELSE
A_OUT<=A_OUT;
END IF;
  END IF;
END PROCESS;

PROCESS(CLK_50M,B_3,DATA_B,B_OUT)
BEGIN
  IF CLK_50M'EVENT AND CLK_50M='1' THEN
IF B_3='1' THEN
B_OUT<=DATA_B;
ELSE
B_OUT<=B_OUT;
END IF;
  END IF;
END PROCESS;

DATA_OUT<=A_OUT;
DATB_OUT<=B_OUT;

END ARCHITECTURE ART;

Testbench文件代码：
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CLK_TB_vhd_tst IS
END CLK_TB_vhd_tst;
ARCHITECTURE CLK_TB_arch OF CLK_TB_vhd_tst IS
-- constants
-- signals
CONSTANT NEWCLK:TIME:=20 NS;
SIGNAL TEST_CLK_10M : STD_LOGIC;
SIGNAL TEST_CLK_20M : STD_LOGIC;
SIGNAL TEST_CLK_50M : STD_LOGIC;
SIGNAL TEST_DATA_A : STD_LOGIC_VECTOR(3 downto 0);
SIGNAL TEST_DATA_B : STD_LOGIC_VECTOR(3 downto 0);
SIGNAL TEST_DATA_OUT : STD_LOGIC_VECTOR(3 downto 0);
SIGNAL TEST_DATB_OUT : STD_LOGIC_VECTOR(3 downto 0);
COMPONENT CLK_TB
PORT (
CLK_10M : in STD_LOGIC;
CLK_20M : in STD_LOGIC;
CLK_50M : in STD_LOGIC;
DATA_A : in STD_LOGIC_VECTOR(3 downto 0);
DATA_B : in STD_LOGIC_VECTOR(3 downto 0);
DATA_OUT : out STD_LOGIC_VECTOR(3 downto 0);
DATB_OUT : out STD_LOGIC_VECTOR(3 downto 0) );
END COMPONENT;
BEGIN
i1 : CLK_TB PORT MAP (
-- list connections between master ports and signals
CLK_10M => TEST_CLK_10M,
CLK_20M => TEST_CLK_20M,
CLK_50M => TEST_CLK_50M,
DATA_A => TEST_DATA_A,
DATA_B => TEST_DATA_B,
DATA_OUT => TEST_DATA_OUT,
DATB_OUT => TEST_DATB_OUT
);
CLK_50M : PROCESS
-- variable declarations
BEGIN
TEST_CLK_50M<='0';
WAIT FOR NEWCLK/2;
TEST_CLK_50M<='1';
WAIT FOR NEWCLK/2;
END PROCESS CLK_50M;
CLK_10M : PROCESS
-- variable declarations
BEGIN
TEST_CLK_10M<='0';
WAIT FOR NEWCLK*5;
TEST_CLK_10M<='1';
WAIT FOR NEWCLK*5;
END PROCESS CLK_10M;
CLK_20M : PROCESS
-- variable declarations
BEGIN
TEST_CLK_20M<='0';
WAIT FOR (NEWCLK*5)/2;
TEST_CLK_20M<='1';
WAIT FOR (NEWCLK*5)/2;
END PROCESS CLK_20M;

DATA_A : PROCESS
-- optional sensitivity list
-- (       )
-- variable declarations
BEGIN
TEST_DATA_A<="0000";
WAIT FOR NEWCLK*5;
TEST_DATA_A<="0001";
WAIT FOR NEWCLK*5;
TEST_DATA_A<="0010";
WAIT FOR NEWCLK*5;
TEST_DATA_A<="0011";
WAIT FOR NEWCLK*5;
TEST_DATA_A<="0100";
WAIT FOR NEWCLK*5;
TEST_DATA_A<="0101";
WAIT FOR NEWCLK*5;
TEST_DATA_A<="0110";
WAIT FOR NEWCLK*5;
TEST_DATA_A<="0111";
WAIT FOR NEWCLK*5;
TEST_DATA_A<="1000";
WAIT FOR NEWCLK*5;
TEST_DATA_A<="1001";
WAIT FOR NEWCLK*5;
TEST_DATA_A<="1010";
WAIT FOR NEWCLK*5;
TEST_DATA_A<="1011";
WAIT FOR NEWCLK*5;
TEST_DATA_A<="1100";
WAIT FOR NEWCLK*5;
TEST_DATA_A<="1101";
WAIT FOR NEWCLK*5;
TEST_DATA_A<="1110";
WAIT FOR NEWCLK*5;
TEST_DATA_A<="1111";
WAIT FOR NEWCLK*5;
END PROCESS DATA_A;

DATA_B : PROCESS
-- optional sensitivity list
-- (       )
-- variable declarations
BEGIN
TEST_DATA_B<="0000";
WAIT FOR NEWCLK*5;

TEST_DATA_B<="0010";
WAIT FOR NEWCLK*5;

TEST_DATA_B<="0100";
WAIT FOR NEWCLK*5;
TEST_DATA_B<="0110";
WAIT FOR NEWCLK*5;
TEST_DATA_B<="1000";
WAIT FOR NEWCLK*5;

TEST_DATA_B<="1010";
WAIT FOR NEWCLK*5;

TEST_DATA_B<="1100";
WAIT FOR NEWCLK*5;

TEST_DATA_B<="1110";
WAIT FOR NEWCLK*5;

END PROCESS DATA_B;

END CLK_TB_arch;
以上代码是正确的，不过在仿真时只能看到源代码中的端口信号，而现在我想看到源代码其中的中间寄存器信号，该怎么办呢？
请问大家用modelsim怎么观察源代码中的A_1,A_2,A_3，B_1,B_2,B_3中间寄存器信号？在testbench中该如何修改呢？

tdyizhen1314 · 发表于 2010-6-10 16:25:30

请教高手指教呀？困扰了很长时间啦！！

eaglelsb · 发表于 2010-6-10 17:09:00

你在SIM窗口点一下你引用的模块，在上面是i1，然后在objects里出现对应的信号了，加进去去看即可。
注意，点击start simulation时要将最下面的enable optimization选项前的勾去掉，

zhourong601 · 发表于 2010-6-10 18:39:09

3#正解

tdyizhen1314 · 发表于 2010-6-10 19:08:11

呵呵是的后来我才找到
3# eaglelsb

tdyizhen1314 · 发表于 2010-6-10 19:09:41

不过我再想说的是有时候为什么里面有很多杂乱的信号，而且有时候仿真不出来那些中间寄存器信号没有数据这又是为什么呢？ 3# eaglelsb

eaglelsb · 发表于 2010-6-10 20:08:25

看出问题来了，你的process敏感信号列表太多，只留CLK，其它去掉再试试。
你继续是想做同步的，那只能在时钟的上升沿打数啊，

wjfblack · 发表于 2011-3-15 13:58:32

回复 3#
貌似不行啊，那个选项是灰色的，根本没法选择

haogong · 发表于 2011-6-26 08:55:40

回复 8# wjfblack

你的问题解决了吗？我的也是灰色。不能勾选啊！

elecmin · 发表于 2011-6-28 11:09:34

这个问题我也一直不会，同求高手指点啊

[讨论] 如何用Modelsim观察源代码中的中间寄存器信号

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