請問關於4x4鍵盤的VERILOG

zhyper4056

代碼如下
module keyscan(clk_scan,clk_debounce,row,col,Key_value);
input [3:0]col;
input clk_scan,clk_debounce; //key_scan:20Hz; key_debounce:200Hz;
output [3:0]row;
output[4:0]Key_value;
wire [3:0]R;
reg [3:0]col_debounced;
reg [3:0]row;
reg [4:0]key_value;
reg [4:0]Key_value;
reg [3:0]key_temp1,key_temp2,key_temp3;
reg [1:0]count;
always @(posedge clk_scan)
begin
Key_value <= key_value;
  count <= count + 1'b1;
end

always @(count)
case(count)
2'b00: row <= 4'b1110;
2'b01: row <= 4'b1101;
2'b10: row <= 4'b1011;
2'b11: row <= 4'b0111;
endcase
always @(posedge clk_debounce)
begin
key_temp1 <= col;
key_temp2 <= key_temp1;
key_temp3 <= key_temp2;
end

assign R = (key_temp1 | key_temp2 | key_temp3);
always @(posedge clk_debounce)
case(R)
4'b0111: col_debounced <= 4'b0111;
4'b1011: col_debounced <= 4'b1011;
4'b1101: col_debounced <= 4'b1101;
4'b1110: col_debounced <= 4'b1110;
default: col_debounced <= 4'b1111;
endcase

always @(row or col_debounced)
case(col_debounced)
4'b1110:
  begin
  case(row)
  4'b1110: key_value = 5'd0;
  4'b1101: key_value = 5'd4;
  4'b1011: key_value = 5'd8;
  4'b0111: key_value = 5'd12;
  default: key_value = 5'd31;
  endcase
  end
4'b1101:
  begin
  case(row)
  4'b1110: key_value = 5'd1;
  4'b1101: key_value = 5'd5;
  4'b1011: key_value = 5'd9;
  4'b0111: key_value = 5'd13;
  default: key_value = 5'd31;
  endcase
  end
4'b1011:
  begin
  case(row)
  4'b1110: key_value = 5'd2;
  4'b1101: key_value = 5'd6;
  4'b1011: key_value = 5'd10;
  4'b0111: key_value = 5'd14;
  default: key_value = 5'd31;
  endcase
  end
4'b0111:
  begin
  case(row)
  4'b1110: key_value = 5'd3;
  4'b1101: key_value = 5'd7;
  4'b1011: key_value = 5'd11;
  4'b0111: key_value = 5'd15;
  default: key_value = 5'd31;
  endcase
  end
default: key_value = 5'd31;
endcase
endmodule

這個output[4:0]Key_value;怎麼會是5個輸出呢?
4X4不是應該4個輸出嗎?
麻煩大哥大姐回答!!

gaurson

我记得好像是一个行扫描配四个列信号吧。印象不深，不能肯定。

rotings

同一个key_value信号不能在两个always块中被赋值，这段代码有错误

gaurson

嗬嗬，楼上的，他区分大小写了。